Chih-Hao SunSHEN-IUAN LIU2018-09-102018-09-102004-0409251030http://scholars.lib.ntu.edu.tw/handle/123456789/310593https://www.scopus.com/inward/record.uri?eid=2-s2.0-1642588269&doi=10.1023%2fB%3aALOG.0000016644.87753.18&partnerID=40&md5=2811a2e2fa9fcef1fe0f88be77da3595A digital synchronous mirror delay combined with an analog delay-locked loop (DLL) is introduced. Under the influence of process, voltage, temperature, and load variations, the conventional digital synchronous mirror delay could not compensate the static phase error because of its digital type and open loop by nature. The proposed circuit can compensate the delay mismatch between the output buffer and the inner stage, which is caused by the different loading conditions. It can improve the noise immunity from supply variations. Moreover, because of the tracking property of the DLL, the static phase error and jitter could also be reduced. The proposed circuit has been fabricated by a CMOS 0.35-μm one-poly four-metal process and the whole chip area is 1.47 × 1.07 mm2 including I/O pad peripherals. The measured peak-to-peak jitter is 16.4 ps at supply voltage of 3.3 V and frequency of 300 MHz. The power consumption of the entire chip is 16.5 mW for analog part and 84 mW for digital part. The comparisons between the proposed circuit and the conventional digital synchronous mirror delay are also demonstrated.Delay-locked loop; Jitter; Static phase error; Synchronous mirror delayCapacitance; CMOS integrated circuits; Computer simulation; Electric potential; Error analysis; Jitter; Mirrors; Power control; Problem solving; Synchronization; Delay-locked loop; Static phase error; Synchronous mirror delay; Phase locked loopsjournal article10.1023/B:ALOG.0000016644.87753.182-s2.0-1642588269WOS:000189015600005