曹恆偉臺灣大學：電機工程學研究所吳駿邦Wu, Chun-PangChun-PangWu2007-11-262018-07-062007-11-262018-07-062006http://ntur.lib.ntu.edu.tw//handle/246246/53149在本論文中主要提出了一個可以使用在超外差系統以及數位中頻系統的可程式化增益放大器。這個放大器具有兩種不同功率的操作模式。在正常功率模式下這個放大器的3dB頻寬可達110MHz以上，而在低功率模式下可達71MHz以上。這個晶片可提供功率增益控制範圍在正常功率模式下為-7.78dB到79.79dB，而在低功率模式下為-7.79dB到80.03dB；在這兩種模式下本晶片皆可提供1dB增益的解析度而僅有±0.4dB誤差。另外還將一個CMOS對數偵測放大器整合在這個可程式化增益放大器中；其偵測範圍為-83dBm到-3dBm且對數準確度在±0.7dB以內。本放大器是以0.35μm 1P4M CMOS製程來實現。晶片裡的運算放大器和固定增益級的偏壓電路中所使用的補償電容是採用MOS元件來實現。量測所得的輸出1dB增益壓抑點為-4dBV；輸出三階交叉點為10.6dBV。晶片操作電壓為3V，在正常功率模式下消耗13mA的電流，在低功率模式下消耗5mA的電流。晶片的面積(包含pad)為1.5×1.5mm2。In this thesis, a CMOS intermediate frequency (IF) programmable gain amplifier (PGA) for superheterodyne and digital-IF systems is proposed. This amplifier could be operated under two different power modes. It maintains a 3dB bandwidth greater than 110MHz under normal power mode and 71MHz under low power mode. And it could provide a power gain control range from -7.78dB to 79.79dB in normal power mode (at 110MHz) and -7.79dB to 80.03dB in low power mode (at 71MHz) with 1dB step resolution and the gain error is within ±0.4dB for both modes. Integrated with this PGA is a CMOS logarithmic successive detecting amplifier with a ±0.7dB logarithmic accuracy for the input signal ranging from -83dBm to -3dBm. The proposed PGA is fabricated in a 0.35μm 1P4M CMOS process. The capacitors used for frequency compensation in the operational amplifier for the bias circuit of the fixed gain stages are realized with MOS capacitors. The gain programming logic circuit and RSSI circuit are also integrated with the proposed PGA. The measured output 1dB compression point is -4dBV, and the third order output intercept point is 10.6dBV. The whole circuit consumes 13mA current when operated in normal power mode and 5mA current when operated in low power mode from a 3V power supply. The chip area, including pads, occupies 1.5×1.5mm2.Table of Contents Abstract Chapter 1 Introduction………………………………………………………... 1 1.1 Wide dynamic range in the wireless communication system…………… 1 1.1.1 Multipath effects…………………………………………………… 2 1.1.2 Distance of the direct path…………………………………………. 4 1.1.3 Dynamic considerations at the transmitter side……………………. 4 1.2 Wide dynamic range in the wired communication system…………… 5 1.3 Signal dynamic range control techniques………………………………. 6 1.3.1 Automatic gain control loop………………………………………... 6 1.3.2 Logarithmic amplifier……………………………………………… 7 1.4 Thesis organization……………………………………………………... 9 Chapter 2 Applications of PGA’s in wireless communication systems…….. 11 2.1 Introduction of the wireless communication systems…………………... 11 2.2 Receiver architecture…………………………………………………… 13 2.2.1 Superheterodyne architecture……………………………………… 14 2.2.2 Direct conversion architecture…………………………………….. 16 2.2.3 Low-IF architecture………………………………………………… 19 2.2.4 Wideband IF architecture with double conversion………………… 21 2.2.5 Digital IF architecture……………………………………………… 22 2.2.6 Summary of receiver architectures………………………………… 24 2.3 Transmitter architecture………………………………………………… 24 2.3.1 Direct conversion architecture……………………………………... 25 2.3.2 Double conversion architecture……………………………………. 26 2.3.3 Offset PLL architecture……………………………………………. 28 2.3.4 Summary of transmitter architectures……………………………… 29 2.4 Dynamic range control techniques……………………………………… 29 2.4.1 Automatic gain control loops………………………………………. 29 2.4.1.1 Decibel-based AGC system…………………………………… 31 2.4.1.2 Non decibel-based AGC system……………………………… 35 2.4.1.3 Summary of AGC systems……………………………………. 37 2.4.2 Logarithmic amplifiers…………………………………………….. 37 2.5 Summary………………………………………………………………... 40 Chapter 3 Circuit design of the programmable gain amplifier…………….. 41 3.1 Wideband amplifier with gain control function………………………… 41 3.2Limiting amplifiers……………………………………………………… 42 3.3 Programmable gain amplifiers………………………………………….. 45 3.3.1 PGA with non-uniform gain distribution…………………………... 46 3.3.2 PGA with uniform gain distribution……………………………….. 47 3.4 The proposed programmable gain amplifier……………………………. 49 3.4.1 Fixed Gain Amplifier Design………………………………………. 51 3.4.1.1 Gain variations of the fixed gain amplifiers…………………… 53 3.4.1.2 The proposed bias circuits against variations………………….. 58 3.4.2 Fine Gain Step Amplifier…………………………………………... 63 3.5 Summary………………………………………………………………... 68 Chapter 4 Circuit design of the integrated RSSI circuit and other considerations……………………………………………………… 71 4.1 The received signal strength indicator circuits…………………………. 71 4.1.1 The diode rectifier circuits…………………………………………. 72 4.1.1.1 The point-contact diodes………………………………………. 73 4.1.1.2 The pn-junction diodes………………………………………… 73 4.1.1.3 The Schottky diodes…………………………………………… 74 4.1.2 The successive detection logarithmic amplifiers…………………... 74 4.1.2.1 The design of the fixed gain amplifiers………………………... 75 4.1.2.2 The design of the rectifier circuits…………………………….. 78 4.2 The design of the offset cancellation circuits…………………………… 83 4.3 Other design considerations…………………………………………….. 87 4.4 Summary………………………………………………………………... 90 Chapter 5 Measurement results of the proposed PGA and RSSI………….. 91 5.1 The measurements of the programmable gain amplifier………………... 92 5.1.1 The measurement of the gain control curve………………………... 92 5.1.1.1 The measured PGA gain control curve and errors…………….. 93 5.1.1.2 The measured gain control linearity of the PGA……………… 96 5.1.2 The measuremed nonlinearity of the PGA…………………………. 96 5.2 The measurements of the RSSI circuits………………………………… 103 5.3 The performance and comparisons of the proposed PGA with some state-of-art PGAs………………………………………………………... 106 5.4 Summary………………………………………………………………... 109 Chapter 6 Conclusion…………………………………………………………. 111 Bibliography n…………………………………………………………1135459425 bytesapplication/pdfen-US可程式化增益放大器對數偵測放大器接收信號強度指示電路programmable gain amplifierlogarithmic detecting amplifierRSSIthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53149/1/ntu-95-F87921058-1.pdf