臺灣大學: 電子工程學研究所黃俊郎李建興Li, Chien-HsingChien-HsingLi2013-04-102018-07-102013-04-102018-07-102011http://ntur.lib.ntu.edu.tw//handle/246246/256795對晶片系統 (System-on-Chips)而言,晶片網路 (NoCs) 是一種相當被看好聯接架構。與傳統的匯流排 (bus) 相比,晶片網路有更好的擴充性(scalability)。然而,晶片網路也對量產測試帶來新的挑戰,其中之一為更加受限的測試點。 在本論文中,我們針對晶片網路中的路由器(router)提出內建自我測試(built-in self-test)與容錯(fault tolerance)技術,其目的在縮短測試時間並提高良率。所提出的內建自我測試其考慮的目標包括先進先出緩衝器(FIFO)與緩衝器之間的組合電路(combinational circuit)這些電路佔據路由器大部份的面積。由於採用高度平行化的測試程序,所需的測試時間非常短。完成自我測試後,診斷模組分析測試結果以決定錯誤的位置。如果錯誤發生在緩衝器,容錯機制將被啓動以避過出問題的暫存器;如果錯誤發生在路由器的輸出或輸入管道,則可以採用可適性的路由器演算法避開這些出問題的部份。 我們以[5]提出的架構為基礎實現了所提出的自我測試與容錯機制。模擬結果顯示可以達到很高的定值錯誤(stuck-at fault)與轉換錯誤(transition fault)涵蓋率,在錯誤診斷也能提供足夠的解析度。Network-on-Chips (NoCs) is a promising interconnect architecture for in System-on-Chips (SoCs) because it exhibits better scalability than the traditional bus architecture. However, NoCs also bring new challenges to manufacturing testing one of which being the limited test access to embedded cores. In this thesis, we propose a built-in self-test (BIST) and fault-tolerance technique for the NoC routers. The proposed BIST scheme covers the FIFO’s and the data path between the FIFO’s of adjacent routers because these components occupy most of the router area. Highly parallelized, the BIST procedure consumes very short test time. A diagnosis module analyzes the BIST results to determine the fault location. If the fault resides in the FIFO’s, the fault tolerance mechanism will be activated so that the faulty register is skipped. For faults that affect one, several, or all input/output channels of a router, one can adopt adaptive routing algorithm to get around the faulty channels or routers. An NoC based on [5] was implemented to validate the proposed techniques. Simulation results show high fault coverage (for stuck-at and transition faults) and high diagnosis resolution with acceptable area overhead.768704 bytesapplication/pdfen-US晶片網路內建自我測試容錯Network-on-ChipsBuilt-in Self-TetFault Tolerance晶片網路中路由器之內嵌自我測試及容錯設計An NoC Router Design with Built-In Self-Test and Fault Tolerance Mechanismthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256795/1/ntu-100-R98943087-1.pdf