黃俊郎臺灣大學：電子工程學研究所陳奕任Chen, Yi-RenYi-RenChen2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57630類比/混模訊號設計測試電路技術仍然不像數位的技術一般被大多採用，其中一個原因是缺乏有效方法來評估它的可信效率。本論文開發了一個製程統計模擬工具來評估類比/混模訊號設計測試電路技術的規格輸出表現分佈。不同於傳統製程參數不相關且與參數獨立的蒙地卡羅模擬方法，本模擬採用參數有相關性而產生更實際的變數來估計，並實現在一個快閃式類比數位轉換器內建自測電路以證實其效率。評估這一個電路技術結果顯示出，此簡易快閃式高速類比數位轉換器電路架構易受製程漂移影響，靜態的內建自測電路架構適合測試靜態規格，而不適於測試動態規格。Unlike their digital counterparts, analog/mixed-signal DfT (Design-for-Test) techniques are still far from being widely adopted. One of the reasons that lead to the low acceptance is the lack of efficient methodologies to evaluate the effectiveness of the AMS (analog/mixed-signal) DfT techniques. In this thesis, we developed a statistical process simulation tool to estimate the performance distribution of an AMS circuit. Unlike traditional Monte-Carlo simulation techniques which disregard the correlation between process and circuit parameters, the proposed statistical simulation tool takes into account the dependency and thus generates a more realistic estimation. The statistical simulation tool is applied to an ADC BIST technique to validate the effectiveness. The results demonstrated that the simple high speed flash ADC is sensitive to process variation, and the static BIST technique is suitable for testing static specifications but not dynamic specifications.Abstract iii 中文摘要 iv Acknowledgments v Table of Contents vi List of Tables vii List of figures viii Chapter 1 Introduction 1 Chapter 2 Preliminaries 3 2.1 Sources of IC performance variations 3 2.2 Categories of process variations 3 2.3 Global (Inter-die) and local (Intra-die) variations 6 2.4 Statistical analysis 7 2.4.1 The main matching parameters 10 2.4.2 Correlation between parameters 11 2.5 Mismatch characterization and modeling 13 Chapter 3 Statistical process variation simulation tool 16 3.1 Flow Chart 16 3.2 The Implementation of local variation 19 3.3 The implementation of global variation 20 3.4 Combining global variation and local variation 21 Chapter 4 Implementation in BIST scheme 23 4.1 ADC characterization 24 4.2 The implementation in ADC BIST circuit 27 4.2.1 Ramp generator 27 4.2.2 Flash ADC 29 4.3 Static and dynamic tests 30 4.3.1 Dynamic FFT test 30 4.3.2 Dynamic sinusoidal Histogram test 31 4.3.3 Static Linear ramp Histogram test 33 4.4 The syntax of program 35 4.5 Results and conclusions discussion 38 Chapter 5 Future work discussion 40 Chapter 6 References 461753754 bytesapplication/pdfen-US統計模擬內建自我測試電路效能評估EvaluationStatistical SimulationBISTthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57630/1/ntu-93-R91943087-1.pdf