Dept. of Electr. Eng., National Taiwan Univ.MIIN-JANG CHENLIANG-GEE CHENCheng, K.-N.K.-N.ChengChen, M.C.M.C.Chen2007-04-192018-07-062007-04-192018-07-061996-081350245Xhttp://ntur.lib.ntu.edu.tw//handle/246246/2007041910032494https://www.scopus.com/inward/record.uri?eid=2-s2.0-0030206740&doi=10.1049%2fip-vis%3a19960541&partnerID=40&md5=cb7111e781aabdec192314ac1efbf065Execution latency and I/O bandwidth play essential roles in determining the effectiveness and the cost of a parallel hardware implementation for block-matching motion estimation algorithms. Unfortunately, almost all traditional architecture designs, e.g. the twodimensional mesh-connected systolic array architecture (2DMCSA), and the tree-type structure (TTS), fail to take these two factors into account simultaneously. As a result, they suffer from either large execution latency or huge input bandwidth requirements. The authors propose a family of tree/linear architectures, which efficiently optimise the total implementation cost by combining the merits of the 2DMCSA and the TTS. Moreover, to facilitate hardware designs, the authors present the tree-cut techniques and the on-chip buffer design method to meet computational demands of various video compression applications. Since the proposed architectures are capable of executing the . exhaustive search and the fast search blockmatching algorithms, they offer relatively flexible and cost-effective hardware solutions for a wide range of video coding systems, including CD-ROM, portable visual communications systems and high-definition TV. © IEE, 1996.application/pdf1072254 bytesapplication/pdfen-USMotion estimation; Video coding; VideoconferencingAlgorithms; Bandwidth; CD-ROM; Computer architecture; Computer hardware; Digital signal processing; Estimation; High definition television; Image coding; Image compression; Optimization; Parallel processing systems; Block matching motion estimation algorithms; Fast search block matching algorithms; Hybrid tree linear array architectures; Two dimensional mesh connected systolic arrays architecture; Image communication systemsjournal article10.1049/ip-vis:199605412-s2.0-0030206740http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032494/1/00537240.pdf