A test clock reduction method for scan-designed circuits

Dept. of Electr. Eng., National Taiwan Univ.Chang, Jau-ShienJau-ShienChangLin, Chen-ShangChen-ShangLin2007-04-192018-07-062007-04-192018-07-061994-10http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032419application/pdf862948 bytesapplication/pdfen-USA test clock reduction method for scan-designed circuitsjournal article10.1109/TEST.1994.527967http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032419/1/00527967.pdf