Huang, T.-Y.T.-Y.HuangLin, Y.-H.Y.-H.LinHUEI WANG2020-06-042020-06-042015https://scholars.lib.ntu.edu.tw/handle/123456789/497538A new topology of power amplifier (PA) is developed in 0.18-μm CMOS. The topology adopts the adaptive bias and pre-distortion linearizer simultaneously. The design of this PA takes back-off efficiency, linear output power, and quiescent power consumption into consideration. After linearization, the proposed PA achieves 6.8% PAE at 6-dB backoff from P1dB, 14.1% PAE at OP1dB, and high linear output power 9.2 dBm with third-order intermodulation distortion (IMD3) of -40 dBc. This circuit shows good performance compared with the published PAs in 0.18-μm CMOS and suitable for high data rate transmission applications. © 2015 IEEE.adaptive bias; CMOS process; K-Band; power amplifier; pre-distortion linearizer[SDGs]SDG7CMOS integrated circuits; Energy efficiency; Topology; Adaptive bias; CMOS processs; High data rate transmission; K bands; Linear output; Linearizers; Pre-distortion; Third order intermodulation distortion; Power amplifiersconference paper10.1109/MWSYM.2015.71668432-s2.0-84946025634https://www.scopus.com/inward/record.uri?eid=2-s2.0-84946025634&doi=10.1109%2fMWSYM.2015.7166843&partnerID=40&md5=16c86e899c0ff20a6b68ad9c2860a728