國立臺灣大學電子工程學研究所黃俊郎2006-07-262018-07-102006-07-262018-07-102004-07-31http://ntur.lib.ntu.edu.tw//handle/246246/20026為了滿足不斷提升的資料頻寬要求，高速序列式（serial）傳送技術已逐漸 取代傳統的並列式（parallel）傳送方法成為主流。然而，各個主要高速通訊標 準（如：Gigabit Ethernet、Infiniband、3GIO、SONET 等）與高頻寬系統backplane 所大量使用的gigabit I/O buffer 對測試而言是極大的挑戰。首先，測試這些 IC 須要昂貴的BER（bit-error-rate）測試儀器組合。過高測試費用與過長的測 試時間使得這個方法不可能在大量生產時使用。此外，目前工業界提高系統整合 度的趨勢也意味著gigabit 序列埠（serial port）將會變成任何IC 的標準介面 模組（I/O macro），所有的IC 生產測試設備將必須配備有符合經濟效益的 gigibit 測試解決方案。因此，發展能在生產測試環境下，有效測試這些gigabit transceiver 的技術成了亟待解決的問題。 在這個子計劃中，我們將針對gigibit I/O transceiver 的jitter testing 提出一個可以有效降低測試成本的可測試性設計技術。主要的目標為量測傳送器 （transmitter）所產生的jitter 與接收器的jitter tolerance。本子計劃為 三年期的計劃。在計劃的第一年，我們將先研究現有的高速序列傳送標準與其 jitter 測試規範與要求。分析這些標準後，我們將先進行系統階層的模擬以決 定一既有彈性（以適合各種標準）又適合在晶片上實現的可測試性設計電路架 構。第二年的主要工作則為各個主要電路的設計與佈局。可測試設計所加入的電 路其噪音與對待測transceiver 的影響也會有詳盡的模擬分析以降低對系統性 能的影響。在第三年，我們將實際下線生產所設計的可測試性電路設計，進行功 能測試以驗證概念與設計的正確性。此外，我們將把所發展的可測試性設計電路 與gigabit transceiver 模組整合，更進一步地驗證我們所發展的技術。The rapid deployment of gigabit I/O buffers for key communication standards, for exmple, Gigabit Ethernet, Infiniband, 3GIO, and SONET, as well as for high bandwidth system backplanes presents several challenges for testing. Testing these ICs requires expensive stand-alone bit-error-rate (BER) test sets. Cost and excessive test time make this approach impossible for volume production. However, the industrial trend toward higher integration levels means that gigabit serial ports can serve as a standard I/O macro for any IC, implying that all existing VLSI production test systems must be retrofitted with cost effective gigabit test solutions. Thus, there is an urgent need for a cost-effective technique to test these gigabit transceivers in volume production. In this project, we intend to provide a low-cost DfT technique for the jitter testing of gigibit I/O transceiver. The goal is to measure the generated jitter at the transmitter output and the jitter tolerance at the receiver input. This sub-project is a 3-year project. In year one, we will first study the current gigabit communication standards and their jitter testing requirements. After analyzing these standards, we will perform system-level simulation to determine the jitter testing architecture that is both flexible and can be realized on chip as the DfT (design-for-test) circuitry. In year two, we will focus on the circuit design of each key component. Detailed circuit-level simulation, noise effects, and interaction with the normal functional circuits will be performed to ensure that the added DfT circuitry has the least impact on the system performance. In year three, a prototype IC will be fabricated. The IC will be verified and tested to validate our ideas. Besides, we will integrate our DfT circuitry to available gigibit I/O macros to further validate our technique.application/pdf159779 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所高速序列資料傳送抖動測試抖動容忍度high-speed serial linkjitter testingjitter tolerancereporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/20026/1/922220E002017.pdf