指導教授：李建模臺灣大學：電子工程學研究所謝弘毅Hsieh, Hung-YiHung-YiHsieh2014-11-302018-07-102014-11-302018-07-102014http://ntur.lib.ntu.edu.tw//handle/246246/263928當測試超大型積體電路晶片時，由於電壓降和電感電壓的影響，電源供應雜訊會導致良率損失。在這篇論文中，我們提出一個考慮電源供應雜訊之動態時序分析器。我們提出的分析器提供合理的準確度和比現存工具還快的速度。因為我們提出的方法是基於線性函數而不是解非線性函數，所以是非常可調整的。實驗結果顯示：在小電路中，與HSPICE相比的誤差小於1%；在大電路中，我們達到比NANOSIM快八倍的速度。我們使用此分析器在一個有一百萬個邏輯閘的測試電路上，並且從三萬一千個測試向量中辨別出369個時序違規的測試向量，這是傳統方法很難找得到的。Due to the effect of IR-drop and Ldi/dt, power supply noise can cause yield loss when testing VLSI chips. In this thesis, we propose a power-supply-noise-aware dynamic timing analyzer, IDEA (IR-Drop-aware Efficient timing Analyzer). The proposed analyzer provides reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on linear functions, instead of solving nonlinear functions. The experimental results show, for small circuits, the error is less than 1% compared with HSPICE. For large circuits, we achieved eight times speed up compared with NANOSIM. IDEA identifies 369 timing-violation test patterns (out of 31K test patterns) for a 1M gate benchmark circuit which are difficult to detect by traditional techniques.Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Technique 3 1.3 Contributions 6 1.4 Organization 7 Chapter 2 Background 8 2.1 PSN Estimation 8 2.2 Extra Gate Delay Calculation 12 2.3 PSN-Aware Timing Analysis 14 Chapter 3 Proposed Techniques 17 3.1 Overall Flow 17 3.2 Charge Model 19 3.3 Extra Gate Delay (Δd) Estimation 22 3.4 Window Partition 31 Chapter 4 Experimental Results 33 4.1 Experimental Setup 33 4.2 IR-drop Only Experiments 34 4.3 IR-drop and Ldi/dt Experiments 38 4.4 Comparison of Dynamic and Static Window Partition 40 Chapter 5 Discussion 42 5.1 False Hazard 42 5.2 Limitation of Multiple Clock Cycles 43 5.3 Interaction between Extra Gate Delay and Event Position 46 5.4 Impact of Different Current Model 50 Chapter 6 Conclusion and Future Work 55 References 571665121 bytesapplication/pdf論文公開時間：2015/09/23論文使用權限：同意無償授權電源供應雜訊電壓降電感電壓電荷動態時序分析器thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/263928/1/ntu-103-R01943142-1.pdf