電機資訊學院: 電子工程學研究所指導教授: 陳中平李映儒Lee, Ying-JuYing-JuLee2017-03-062018-07-102017-03-062018-07-102015http://ntur.lib.ntu.edu.tw//handle/246246/276253This dissertation proposes a pre-switching technique for high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs), and a low-power and low-cost On-Off Keying(OOK) transceiver for powerline communication (PLC) system. The pre-switching method speeds up the SAR ADC. The OOK modulation not only save the power consumption but also save the area cost. Furthermore, the OOK transceiver improves the reliability of PLC system. A 10-bit 100MS/s SAR ADC with pre-switching method was implemented in TSMC 90nm CMOS technology. In measurement results, when the SAR ADC operate at 50MS/s sampling rate with 20MHz input frequency, the measured ENOB and SFDR is 8.28 and 64.72dB. In 100MS/s sampling rate with 50MHz input frequency, the measured ENOB is 7.77 and SFDR is 58.66dB respectively. The ADC consumes 1.8mW from 1-V supply when the sampling rate is 100MS/s, the resulting figure of merit (FOM) is 79fJ/conversion-step. The OOK PLC transceiver was fabricated in TSMC 0.25um CMOS technology. In measurement results, the maximum data rate is 45Kbps. When data rate is 10Kbps, the power consumption is 25mW. Moreover, the transceiver can recover the NRZ data by power line with 1 meter and 5 meters.5557287 bytesapplication/pdf論文公開時間: 2017/8/11論文使用權限: 同意有償授權(權利金給回饋學校)逐漸趨近式類比數位轉換器電力線通訊系統收發器analog to digital convertertransceiveron off keyingPLCthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/276253/1/ntu-104-R01943117-1.pdf