陳良基臺灣大學：電子工程學研究所林修身Lin, Siou-ShenSiou-ShenLin2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57365移動估計是視訊壓縮裡重要的關鍵技術，能有效的刪除視訊資料時間上的多餘性，藉以達到壓縮目的。移動估計並且廣泛的為各種視訊壓縮標準所採納。然而，移動估計需要相當龐大的運算量，使得需要電池供電的行動視訊應用發展受到限制。在這篇論文裡，針對高階的行動視訊裝置以及具能量感知的行動視訊裝置分別提出了解決方案。 針對高階的行動視訊裝置，提出了一個低功率的全搜尋移動估計處理器。在這章節裡，針對全搜尋區塊比對演算法提出了一個新的平行樹狀架構。平行樹狀架構能有效的利用平行候選區塊點的空間相關性，有效的消除了資料量的存取。搭配部分誤差消除法，每個區塊所需要處理的時脈減少了50%以上以達到低功率消耗的目的。此外，這架構在消除不必要運算時，沒有管線化延遲，以及在陣列架構裡常常有許多移位暫存器功率消耗問題及不必要記憶體存取的問題。 在晶片實作上，使用了UMC 0.18 um CMOS 1P6M 製程，在CIF 每秒30 張下，根據量測結果，20 MHz 1.35V 時消耗13.5 mW。因此，提出的架構非常適合需要低功率且高品質的高階即時行動視訊壓縮運用。 另一方面，針對需要能量感知特性的行動視訊應用，從演算法層次的分析到架構層次的考慮，提出了多重模式具能量感知之可重組化移動估計處理器。在演算法層次，利用視訊信號的特性，提出了兩個內容感知的判斷準則以決定移動向量的複雜度。根據這兩個判斷準則以及不同演算法的組合，在不同的運算量限制下以及不同運算品質提出了四種不同的模式。此外，提出的內容感知判斷準則在各種運算量限制下，能夠利用不同演算法的選擇使得運算品質達到最好。在架構 層次上，提出了可重組化的移動估計架構，能夠即時切換不同的演算法，且只需一些額外電路。 在晶片實作上，使用了UMC 0.18 um CMOS 1P6M 製程，在CIF 每秒30 張下，根據模擬結果，不同的模式分別消耗51.27 mW、24.88 mW、13.76 mW 以及8.46 mW，而平均的運算品質分別下降0 dB、0.0036 dB、0.01 dB、以及0.16 dB。因此，提出的處理器非常適合需要能量感知特性的視訊壓縮系統。Motion estimation is the fundamental technique of video coding, which effectively reduces the temporal redundancy among video sequences, and it is widely used in nowadays video compression standards. However, it takes huge amount of computation to perform the motion estimation, which makes the battery-powered mobile video application difficult. In this thesis, two solutions are proposed for the high-end mobile video device and the power-aware mobile video system respectively. For the high-end mobile video device, the low-power full search motion estimation processor is developed. In this section, a novel low-power parallel tree architecture is proposed for the full search block-matching motion estimation. The parallel tree architecture exploits the spatial data correlations between parallel candidate block searches for data sharing, which effectively eliminates huge amount of data access bandwidth while consumes fewer hardware resources compared with array-based architectures. Combining with adaptive parallel partial distortion elimination algorithm, the required average clock cycle count for each macroblock search can be greatly reduced to below 50% to achieve low-power operation. Besides, this architecture can also eliminate redundant computation without pipeline latency and excess power consumption caused by register data shifting and redundant memory accessing in array-based architectures. In chip implementation, the power consumption is 13.5 mW at 20MHz and 1.35V under the UMC 0.18 µm CMOS 1P6M process with 667K transistor counts. The proposed chip is suitable for high-end real-time mobile video encoding system, which desires high-quality video but low power consumption. For the power-aware mobile system, the multi-mode power-aware reconfigurable motion estimation processor is implemented. In the algorithm level, by exploiting the characteristics of video signal, two content-aware decision criteria are proposed to identify the complexity of motion vectors. Based on these two decision criteria as well as different combinations of motion estimation algorithms, four different modes are proposed to vary the computation resources under different power constraints dynamically. Besides, the proposed decision criteria also enable the maximization of quality under each power constraint by quality-driven diversity-based search approach. In the architecture level, by analyzing the similarity between different motion estimation algorithms, the power-aware reconfigurable motion estimation architecture, which can switch different algorithm in real-time requirement easily, is proposed with small hardware overhead. The processor is fabricated under the UMC 0.18 µm CMOS 1P6M process with 546K transistor counts. According to our simulation results, the post-layout gate-level power consumptions are 51.27 mW, 24.88 mW, 13.76 mW , and 8.46 mW for each mode respectively, and with only 0dB, 0.0036dB, 0.01dB, and 0.16dB average quality degradation. Therefore, the proposed processor is well-suited for mobile video coding systems that desire power-awareness feature.目錄 摘要......................................................2 第一章、緒論..............................................3 第二章、移動估計之相關研究................................4 第三章、低功率全搜尋移動估計處理器........................5 第四章、多重模式具能量感知之可重組化移動估計處理器........6 第五章、晶片實作..........................................7 第六章、結論..............................................8 Contents Abstract xi 1 Introduction 1 1.1 Video Coding Systems 1 1.2 Concept of Motion Estimation 2 1.3 Challenge of VLSI Implementation for Motion Estimation 3 1.4 Research Contributions 4 1.4.1 Low-Power Full Search Motion Estimation Processor 4 1.4.2 Multi-Mode Power-Aware Reconfigurable Motion Estimation Processor 4 1.5 Thesis Organization 5 2 Related Researches of Motion Estimation 7 2.1 Existing Algorithms of Motion Estimation 7 2.1.1 Full Search 7 2.1.2 Fast Full Search 8 2.1.3 Fast Search 9 2.2 Previous Architectures of Motion Estimation 13 2.2.1 Array-Based Architectures 13 2.2.2 Tree-Based Architectures 15 3 Low-Power Full Search Motion Estimation Processor 19 3.1 Increasing the Parallelism in the Sub-Tree Architecture 19 3.1.1 Increasing the Parallelism Vertically 19 3.1.2 Increasing the Parallelism Horizontally 20 3.2 Proposed Parallel Tree Architecture 22 3.2.1 FS Motion Estimation 22 3.2.2 Parallel Tree 22 3.2.3 Minimum Comparing Tree 23 3.3 Low-power operation by exploiting the PDE 23 3.3.1 Modified Spiral Scanning and Parallel Predicted Candidate 23 3.3.2 Spatial Correlation between Neighboring Candidates 25 3.3.3 Different Parallelism in the Parallel Tree 26 3.4 Architecture of the Low Power Full Search Motion Estimation Processor 28 3.4.1 Block Diagram of the Processor 28 3.4.2 Analysis of the RAM Buffers 31 3.4.3 The Flow of the Low-Power Full Search Motion Estimation Processor 34 3.5 Compared with Other Architectures 35 4 Multi-Mode Power-Aware Reconfigurable Motion Estimation Processor 41 4.1 The Concept of Power-Aware Computing 41 4.1.1 Introduction of Power-Aware Computing 41 4.1.2 Challenge of Power-Aware Computing 41 4.2 Proposed Content-Aware Diversity-Based Motion Estimation Algorithm 43 4.2.1 Techniques for Motion Estimation Computation Reduction 43 4.2.2 The Variance of Motion Vectors 44 4.2.3 The Accuracy of Predicted Motion Vectors 46 4.2.4 Content-Aware Diversity-Based Motion Estimation Algorithm 52 4.2.5 Simulation Results 56 4.3 Power-Aware Reconfigurable Motion Estimation Architecture 62 4.3.1 The Similarity between Different Algorithms 62 4.3.2 Block Diagram of the Processor 62 4.3.3 The Flow of the Multi-Mode Power-Aware Reconfigurable Motion Estimation Processor 68 4.4 Compared with Other Architectures 68 5 CHIP Implementation 71 5.1 Low Power Techniques 71 5.1.1 Clock Gating 71 5.1.2 Operand Isolation 74 5.1.3 Voltage Scaling Down 75 5.2 DesignFlow 75 5.3 Design for Test Considerations 78 5.4 Implementation of Low-Power Full Search Motion Estimation Processor 80 5.5 Implementation ofMulti-Mode Power-Aware Reconfigurable Motion Estimation Processor 81 6 Conclusion 91 7 Appendix 93 7.1 Experimenting on Adaptive Decimation 93 7.2 Experimenting on Pixel Truncation 9415248195 bytesapplication/pdfen-US移動估計行動視訊功率感知Power-AwareMotion EstimationMobilethesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57365/1/ntu-93-R91943081-1.pdf