李泰成臺灣大學：電子工程學研究所孫致彬Sun, Chih-PinChih-PinSun2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57450人與人之間的行動通訊發展的相當快，而新的無線通訊技術和協定也很快的被熱心的人們採用。因為RF技術的進步，數位電路的發展，行動通訊技術工業正在以倍數的成長。而行動通訊所需要的通訊端硬體，也因為VLSI技術的改善與進步，變的更小，更便宜，攜帶更方便，也更可靠。 對於行動通訊的接收機設計中，直接降頻接收機是一個很重要的架構。因為比較有利於整合於晶片當中。但是直接降頻接收機有許多的問題，直流電壓偏差是其中較嚴重的一項。它會造成整個接收機的敏感度降低，而且降低整個基頻電路的動態區域。許多直流電壓偏差的消除技巧已經研究出來，可以增加接收機的效能，並提供足夠大的動態區域。 在本論文，我們描述一個可以應用在寬頻序列分工多重擷取系統的直流電壓偏差消除技巧。系統模擬結果顯示，此直流電壓偏差消除電路的截止頻率必須在 10 kHz 以下。另外，一個通道選擇濾波器也被整合在同一個的晶片當中。此直流電壓消除電路是以頻率相關負電阻為基礎，此負載可作為一個直流回授迴路，校正在輸入端的偏差電壓。模擬結果顯示，它可以只需要普通伺服回路四分之ㄧ的電容即可以提供足夠的衰減度和截止頻率。此晶片只使用1.8 V的電壓源，消耗8 mW，並使用0.18毫微米CMOS製程來設計此晶片。The ability to communicate with people on the move has evolved remarkably, and new wireless communications methods have been enthusiastically adopted by people throughout the world. The mobile radio communications industry has grown by orders of magnitude because of the digital and RF circuit fabrication improvements, new large-scale circuit integration and other miniaturization technologies which make portable radio equipment smaller, cheaper and more reliable. For mobile receiver design, direct-conversion receivers are most important architecture for monolithic integration. But, DC offsets in direct-conversion receivers is one of the critical problems. Lots of the offset cancellation techniques are developed to enhance the receiver performance, and provide large dynamic range for the baseband circuit. In this thesis, we describe the implementation and measurement results of offset cancellation architecture for WCDMA mobile system. A system simulation indicates the offset cancellation must provide a 10-kHz corner frequency. A channel selection filter is also integrated in the chip to provide 40-dB adjacent channel selectivity. The offset cancellation is composed of a FDNR based load to provide a DC feedback loop to correct the offset voltage. Simulation results show that only quarters of capacitors can be used to provide the same corner frequency and attenuation compared with the conventional servo loop. The chip consumes 8 mW from a 1.8-V supply and is fabricated in a 0.18-μm CMOS technology.Table of Contents Table of Contents I List of Figures V List of Tables IX Chapter 1 Introduction 1 1.1 Motivation and Research Goals 1 1.2 Thesis Organization 2 Chapter 2 Basic Concepts 5 2.1 Direct-Conversion Receivers 3 2.1.1 Basic components and design issues 3 2.1.2 DC offsets in direct-conversion receivers 4 2.2 DC-Offset Cancellation in Direct-Conversion Receivers 5 2.2.1 AC coupling 5 2.2.2 Digital calibration in offset cancellation 5 2.2.3 Offset cancellation in TDMA system 6 2.2.4 Servo loop 7 2.3 Channel Selection Filter 8 2.3.1 Lowpass filter 8 2.3.2 Second-order filter (Biquad) 10 2.3.3 Maximum flat magnitude response 11 2.3.4 Determination of filter order 13 2.3.5 Lossy and lossless integrators 14 Chapter 3 System Architecture of a WCDMA Receiver with Offset Cancellation 17 3.1 Introduction 17 3.1.1 Second generation (2G) cellular networks 17 3.1.2 Evolution to 2.5G mobile radio networks 19 3.2 Third Generation (3G) Wireless Networks 21 3.2.1 Evolution of 3G wireless networks 21 3.2.2 CDMA2000 21 3.2.3 TD-SCDMA 22 3.3 Receiver Baseband Design for WCDMA Mobile 23 3.3.1 Introduction of WCDMA 23 3.3.2 WCDMA characteristics 23 3.3.3 Noise and linearity requirements 25 3.4 System Simulation Results 28 Chapter 4 An Offset Cancellation Technique for WCDMA Direct-Conversion Receivers 33 4.1 Architecture 33 4.2 Principles of Offset Cancellation 33 4.3 FDNR in Offset Cancellation 34 4.3.1 Frequency-dependent negative resistance 34 4.3.2 FDNR in the offset cancellation loop 35 4.3.3 GIC basic concepts 38 4.3.4 Modified FDNR 39 4.3.5 Floating FDNR 40 4.3.6 Opamps used in the FDNR 41 4.4 Circuit Blocks Implementtaion 41 4.4.1 Gm cells in offset cancellation 41 4.4.2 Common-mode feedback circuit 42 4.4.3 Summing circuit 43 4.4.4 The offset cancellation circuit design summary 44 4.4.5 FDNR noise analysis 46 4.5 Transistor Level Simulation Results 47 Chapter 5 Channel Selection Filter 49 5.1 LC Ladder Filter 49 5.2 Leapfrog Filter 51 5.2.1 Developing the leapfrog architecture 51 5.2.2 Realization of the leapfrog filter 52 5.3 Butterworth Filter with Leapfrog Architecture 55 5.3.1 Opamps used in the filter design 55 5.3.2 Variable gain 56 5.3.3 The complete filter circuit 57 Chapter 6 Measurement Results and Conclusion 61 6.1 Measurement Results 61 6.1.1 Test setup 61 6.1.2 Offset cancellation measurement results 62 6.1. 3 Channel selection filter measurement results 63 6.2 Conclusion 64 6.3 Further Discussion 65 Finite gain of the opamps in FDNR 65 Bibliography 67 List of Figures Chapter 1 Chapter 2 Figure 2.1 Direct-conversion receivers architecture with quadrature downconversion. 3 Figure 2.2 (a) Self-mixing of LO signal. (b) Self-mixing of a strong interferer. 4 Figure 2.3 AC coupling in signal path. 5 Figure 2.4 Digital calibration in offset cancellation. 6 Figure 2.5 Offset cancellation in TDMA system. 7 Figure 2.6 Servo loop. 7 Figure 2.7 Lowpass magnitude response. 8 Figure 2.8 Practical filter attenuation specifications to be met by continuous functions α (ω) (dashed lines). 9 Figure 2.9 Other lowpass filter magnitude responses. 10 Figure 2.10 Definitions of parameters related to pole positions. 11 Figure 2.11 Poles of T(s)T(-s) for n = 2, 3, 4. 13 Figure 2.12 Miller integrator. 14 Figure 2.13 Noninverting integrator. 15 Chapter 3 Figure 3.1 Various upgrade paths for 2G technologies. 20 Figure 3.2 Duplexer leakages from the transmitter to the receiver. 26 Figure 3.3 Third order intermodulation. 27 Figure 3.4 IIP2 calculation. 27 Figure 3.5 System architecture of a transmitter. 28 Figure 3.6 System architecture of a receiver. 28 Figure 3.7 Spectrum of the WCDMA signal with a 5 MHz offset interference. 29 Figure 3.8 (a) Tx I signal. (b) Rx I signal. 29 Figure 3.9 (a) Tx Q signal. (b) Rx Q signal. 30 Figure 3.10 Downconversion signal with offset cancellation. 30 Figure 3.11 Downconversion signal without offset cancellation. 30 Chapter 4 Figure 4.1. Offset cancellation architecture. 33 Figure 4.2. Frequency-dependent negative resistance RC-network. 34 Figure 4.3. Circuit symbol for FDNR. 35 Figure 4.4. FDNR in series with a capacitor. 35 Figure 4.5. Offset cancellation with FDNR in series with a capacitor. 36 Figure 4.6. Offset cancellation with negative Gm to enhance FDNR. 37 Figure 4.7. Two port network to derive inductive impedance. 38 Figure 4.8. The general impedance converter (GIC) circuit in forward direction. 39 Figure 4.9. The modified FDNR RC network. 39 Figure 4.10. Floating FDNR using in differential circuit. 41 Figure 4.11. Opamps used in the FDNR. 41 Figure 4.12. Folded cascode Gm cell. 42 Figure 4.13. Common-mode feedback circuit. 42 Figure 4.14. Summing circuit. 43 Figure 4.15. Complete circuit architecture. 44 Figure 4.16. Noise model of the FDNR. 46 Figure 4.17. Thevenin equivalent circuit for analysis the output noise voltage of FDNR. 46 Figure 4.18. AC response of the offset cancellation. 48 Figure 4.19. Step response of the offset cancellation. 48 Chapter 5 Figure 5.1. Sixth-order all-pole lowpass ladder. 49 Figure 5.2. The ladder with series impedance and shunt admittance. 50 Figure 5.3. A passive ladder network. 51 Figure 5.4. A block diagram of a simulation of the network of Fig. 5.3. 52 Figure 5.5. Inverting summing lossy integrator. 53 Figure 5.6. Noninverting summing lossy integrator. 53 Figure 5.7. Active realization of the lowpass ladder. 55 Figure 5.8. Two stage opamp. 55 Figure 5.9. Inverting integrator. 56 Figure 5.10. Sixth-order Butterworth filter. 57 Figure 5.11. Channel selection filter ac response. 58 Chapter 6 Figure 6.1. Measuring environment. 61 Figure 6.2. Testing PCB board. 62 Figure 6.3. Die photo of the chip. 62 Figure 6.4. Measured offset cancellation result ac response. 63 Figure 6.5. Measured transient response. 63 Figure 6.6. Channel selection filter ac response. 64 Figure 6.7. Finite gain of the opamps in FDNR. 65 List of Tables Chapter 1 Chapter 2 Chapter 3 Table 3.1. Specifications of Leading 2G Technologies. 18 Table 3.2. UMTS standard characteristics. 24 Table 3.3. Test parameters for reference sensitivity. 25 Chapter 4 Table 4.1. The devices sizes of the summing circuit in Fig. 4.14. 45 Table 4.2. Comparison of the three continuous-time offset cancellation techniques. The corner frequencies are all set at 5 kHz, and all the circuits are for differential I/Q path. 45 Chapter 5 Table 5.1. Programmed gain control at each stage. 57 Table 5.2. Filter resistance parameters. 58 Chapter 6 Table 6.1. Chip performance summary. 642218039 bytesapplication/pdfen-US基頻電路直流偏壓偏差消除直接降頻接收機baseband circuitDC offset cancellationDirect conversion receiverthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57450/1/ntu-94-R92943025-1.pdf