A 1.5 V BiCMOS dynamic subtracter circuit for low-voltage BiCMOS CPU VLSI

Dept. of Electr. Eng., National Taiwan Univ.Chen, Y.G.Y.G.ChenKuo, J.B.J.B.Kuo2007-04-192018-07-062007-04-192018-07-061994-08http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032409application/pdf174188 bytesapplication/pdfen-USA 1.5 V BiCMOS dynamic subtracter circuit for low-voltage BiCMOS CPU VLSIjournal article10.1109/MWSCAS.1994.519014http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032409/1/00519014.pdf