臺灣大學: 電子工程學研究所胡振國鄭任遠Cheng, Jen-YuanJen-YuanCheng2013-04-102018-07-102013-04-102018-07-102012http://ntur.lib.ntu.edu.tw//handle/246246/256729在本研究中，我們首先針對在金氧半電容元件中超薄氧化層(<4.0nm)所發現的由量子穿隧效應所引起的深空乏(deep depletion)特性，藉由電壓-電容量測法進行全面探討。經由不同的二氧化矽超薄氧化層(2.0 to 2.8nm)實驗結果顯示,深空乏起始電壓會隨著氧化層厚度而增加；進一步藉由氧化層崩潰的實驗檢視，經固定電壓檢測(constant voltage stress)，氧化層崩潰後，深空乏區的起始電壓將會減少(提早發生)。藉由所探討在電容-電壓測量深空乏區的物理特性，我們提出在深空乏區特有的區域空乏電容模型(Local depletion capacitance (LDC) model)，此模型可進行並量化金氧半電容元件中的電荷不均勻分布特性。藉由此模型我們進一步發現，電荷均勻度在二氧化矽元件中隨著氧化層厚度而上升，而在高介電係數二氧化鉿元件中隨著厚度而下降。結合前述所分析穿隧與不均勻引發深空乏現象，我們更進一步探討在高頻電壓電容曲線中由空乏-反轉區(depletion-inversion)至深空乏區的曲線彎曲下降的特殊現象，藉由邊緣電場效應(Edge Fringing Effect)的分析，我們結合了量子力學高頻電容理論，以及前述所提到區域空乏電容模型，進而成功分析並描述電容電壓從空乏-反轉區到深空乏區的曲線向下彎曲現象。同時亦提出邊緣電場效應所引起的元件周長(元件邊緣)的強化深空乏區概念。 藉由元件週長強化空乏區的理論，我們設計並實現基於邊緣電場效應所產生的金氧半穿隧光二極體(MOS tunneling photodiode)的雛形，藉由直接發現在二氧化鉿元件中其擁有更強化深空乏區(與二氧化矽相比)的證據，我們可提高原先同等校電容厚度(Equivalent Oxide Thickness, EOT)下二氧化矽(一百倍)的穿隧二極體的靈敏度達到三千倍之多。 在最後附錄部份，我們探討藉由國科會千里馬計畫所贊助於加州柏克萊大學電機工程與電腦科學系的元件團隊所進行的研究計畫。基於未來縮小節點並降低功耗的需求，著眼於次臨限斜率(sub-threshold swing)為主的設計概念，將負電容場效應電晶體(negative capacitance MOSFET)結合最新在鐵電負電容電晶體發現的無遲滯(non-hysteretic)現象，藉著全新的超薄矽置放於導體上方架構(thin silicon on conductor)的概念，我們成功突破了Boltzmann limits (60mV/dec)的限制，藉由TCAD軟體的輔助證實，理論模擬可以達到在無應力協助下，平均次臨限斜率能有28.3mV/dec的表現。In this work, a comprehensive study on tunneling induced deep depletion (DD) behavior with ultra-thin oxide (2.0 to 2.8nm) of MOSCAPs was investigated from C-V curves experimentally. With comparing the C-V and J-V diagrams simultaneously, it was found that the initiation voltage of DD increases with EOT and early occurrence of DD was observed after oxide breakdown. A new methodology named local depletion capacitance (LDC) model was introduced to evaluate the electrical uniformity quantitatively via C-V in DD region. It was found that the electrical uniformity increases with EOT for SiO2 MOSCAP. In contrast, the HfO2 MOSCAP shows opposite result to SiO2, the electrical uniformity decrease with the EOT. We then therefore extended the tunneling induced DD concept to study the downward C-V from depletion-inversion to DD, the edge fringing effect (EFE) was successfully characterized by EFE based quantum-mechanical C-V incorporated LDC model approach. The result suggested the EFE has a great impact on the device perimeter, i.e., enhanced the edge depletion width of the device. With utilizing the EFE enhanced edge depletion concept, the perimeter-light-absorption (PLA) type MOS tunneling photodiode prototype was demonstrated. Via direct observation enhanced DD at edge via HfO2/SiO2, the sensitivity was recognized a greater improvement (3,000x) than previous research using SiO2 as dielectric (100x). In the appendix of this work, we briefly reported the research in UC Berkeley (with Device Group, Department of Electrical Engineering and Computer Science), funded by National Science Council (NSC) of Taiwan government. Owing to extreme scaling trend, a tremendous low power demand was aroused. The sub-threshold swing (SS) oriented design brings birth to negative-capacitance MOSFET (NCFET) at Berkeley. A non-hysteresis mode (from the latest study in IEDM 2011) in NCFET was adopted here with the whole new thin-silicon-on-conductor (TSOC) architecture. The sub-60mV/dec (Boltzmann’s Limits) can be achieved experimentally, i.e., the 28.3mv/dec operation was obtained without additional strain enhancement.140 bytestext/htmlen-US深空乏金氧半電容元件不均勻度高介電係數氧化層光穿隧二極體邊緣電場效應次臨限斜率負電容電晶體鐵電材料deep depletionMOSCAPsnon-uniformityhigh-k dielectrictunneling photodiodeedge fringing effectsub-threshold swingnegative capacitance MOSFETferroelectric materialsthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256729/1/index.html