H. P. ChenJAMES-B KUO2018-09-102018-09-102004-12https://www.scopus.com/inward/record.uri?eid=2-s2.0-27644494747&partnerID=40&md5=bfc52dc8782597b4145b9654dc2c342cThis paper reports a novel 0.8V CMOS true-single-phase-clocking (TSPC) adiabatic differential cascode voltage switch (DCVS) logic circuit with the bootstrap technique for low-power VLSI. Via the pass transistors and compensating transistors, TSPC scheme has been obtained for easy clocking. Using the capacitance coupling from the bootstrap transistors, this 0.8V TSPC adiabatic DCVS logic circuit with the bootstrap technique consumes 31% less energy as compared to the one using the clocked adiabatic latch (CAL) approach. © 2004 IEEE.[SDGs]SDG7Capacitance; CMOS integrated circuits; Logic circuits; Transistors; Capacitance; Clocks; CMOS integrated circuits; Computer circuits; Logic circuits; Low power electronics; Timing circuits; VLSI circuits; Bootstrap transistors; DCVS logic circuit; True-single-phase-clocking (TSPC); VLSI circuits; Statistical methods; Bootstrap technique; Bootstrap transistors; Capacitance coupling; Clocking schemes; Differential cascode voltage switch logic; Energy; Low Power; Pass transistors; True-single-phase-clockingconference paper10.1109/icecs.2004.13996432-s2.0-27644494747