Hsiao, K.-J.K.-J.HsiaoTAI-CHENG LEE2020-06-112020-06-11200801936530https://scholars.lib.ntu.edu.tw/handle/123456789/498476https://www.scopus.com/inward/record.uri?eid=2-s2.0-49549103575&doi=10.1109%2fISSCC.2008.4523283&partnerID=40&md5=0c1a91c2c8863d4e78b4ea006204f59fWe demonstrate a distributed DLL with low jitter and high phase accuracy for multiphase clock generation. The frequency of operation ranges from 8 to 10GHz. The measured RMS jitter is 293.3fs and the maximum phase mismatch is 1.4ps. The distributed DLL occupies 0.03mm2 active area in a 90nm CMOS technology and draws 15mA from a 1.0V supply. ©2008 IEEE.Clocks; Jitter; 90-nm cmos; Active area; Frequency of operation; Low jitters; Maximum phase; Multiphase clock; Phase accuracy; Phase clocks; Delay lock loopsconference paper10.1109/ISSCC.2008.45232832-s2.0-49549103575https://www.scopus.com/inward/record.uri?eid=2-s2.0-49549103575&doi=10.1109%2fISSCC.2008.4523283&partnerID=40&md5=0c1a91c2c8863d4e78b4ea006204f59f