王勝德臺灣大學：電機工程學研究所廖偉益Liao, Wei-YiWei-YiLiao2007-11-262018-07-062007-11-262018-07-062007http://ntur.lib.ntu.edu.tw//handle/246246/53351在這篇論文中，我們提出了一個決定軟硬體分割的預測法則，藉由這個預測法則可以在混合型軟硬體平台中決定是否進行分割及最佳的分割組合，主要的作法是希望藉由硬體來加速整體的執行速度，再透過由速度的提昇達到能源消耗的減低，在這樣的作法中我們必須要克服硬體電路的高電源消耗問題以及多餘的軟硬體溝通時間造成的電源消耗。在系統平台的應用上使用不同軟核 (Soft Core) 來和硬體電路做搭配，整個系統透過可程式化邏輯閘陣列 (Field-Programmable Gate Array；FPGA) 來建立出來，最後實作在 DE2 這個開發板上。 我們使用了 Quartus II 軟體內建的可程式單晶片系統編輯器 (System On a Programmable Chip；SOPC Builder) 來建立出可計算執行時間的模組，透過這樣的模組再搭配上 Quartus II 的PowerPlay Power Analyzer Tool 來計算整體的消耗能 源，發現在良好的軟硬體分割下速度可以提昇約 2.10％~ 91.96％ ，提昇速度的多寡受分割情況及硬體加速情況的影響，再經由實驗及我們所設計的軟硬體分割預測法則來比較分析預測法則準確率，發現準確率可以達93.88％，最後可用我們尋找最佳分割的經驗法則來找出電源消耗量最省的分割組合。In this paper, we present a power-aware partitioning approach for a class of embedded systems that are modeled by program graphs. The goal of approach is to find the most appropriate partition to minimize the considered energy consumption as well as the execution time of the system. The main concept of the approach is the critical software parts are accelerated on hardware to reduce the total system energy. The proposed approach is based on the estimation of energy consumption of hardware and software blocks and a heuristic rule to determine the feasible partition. In addition to the software and hardware parts, we also take into the required communication between the hardware and software blocks of a partition. A embedded system composed of soft cores and coarse-grain reconfigurable hardware is considered and implemented on an FPGA, platform called DE2. We use the Altera SOPC Builder to build systems and evaluate embedded systems and employ the PowerPlay Power Analyzer tool to estimate system energy consumption. As compared to all-software implementation, the hardware/software partitioning results show that we can obtain up to 91.96% speedups, and up to 28.15% energy savings. The quality of the proposed partitioning approach is also testified by the high accuracy rate of 93.88% when comparing estimated results with experiment result.致謝 .................................................... I 中文摘要 ............................................... II ABSTRACT .............................................. III 圖目錄 ................................................. VI 表目錄 ................................................ VII 第一章、緒論 ............................................ 1 1.1 主要動機 ............................................ 1 1.2 相關研究 ............................................ 4 1.3 總結 ............................................... 11 第二章、系統架構及軟核 ................................. 12 2.1 可程式單晶片系統 (SOPC) ............................ 12 2.2 NIOS II 軟核簡介 ................................... 13 第三章、軟硬體分割 ..................................... 15 3.1 軟硬體分割系統 ..................................... 15 3.2 軟硬體分割目的及方法 ............................... 17 3.3 從功能函數層級來決定系統中應該以純軟體實作的區塊.....20 3.4 軟硬體分割法則及參數 ............................... 24 3.5 推測最佳分割組合 ................................... 31 3.6 分割預測法則範例 ................................... 33 3.7 總結 ............................................... 37 第四章、實驗結果 ....................................... 38 4.1 實驗使用平台 ....................................... 38 4.2 使用AVALON 界面的TIMER 核心以及POWERPLAY POWER ANALYZER 工具來評估系統 ................................ 39 4.3 效能評估及功率計算 ................................. 42 4.3.1 系統整體效能以及消耗電源 ......................... 42 4.3.2 系統能源消耗量計算 ............................... 43 4.4 實驗結果 ........................................... 44 4.4.1 硬體加速對執行時間及消耗功率的影響 ............... 44 4.4.2 分割預測法則準確率 ............................... 49 4.4.3 推測最佳分割組合的效果 ........................... 50 參考文獻： ............................................. 53993969 bytesapplication/pdfen-US軟硬體分割軟核FPGA電源消耗量電源估計Hardware/software partitioningsoft core processorenergy estimation[SDGs]SDG7thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53351/1/ntu-96-R94921110-1.pdf