Chen, Chia MinChia MinChenHong, Yu MengYu MengHongTSUNG-HSIEN LIN2023-08-072023-08-072023-01-019798350334166https://scholars.lib.ntu.edu.tw/handle/123456789/634455This paper presents a sub-sampling phase-locked loop (SSPLL) with the proposed digital counter-based frequency-locked loop (FLL) to achieve agile and robust frequency locking. With a 20-MHz reference frequency, the measured SSPLL in-band phase noise at 2.42 GHz is -110 dBc/Hz; the reference spur is -50 dBc. Fabricated in a 90-nm CMOS and operated from a 1.2-V supply, the SSPLL including the proposed FLL consumes 14.5 mW while the power consumption is reduced to 3 mW when the FLL is turned off. Under a 500-mV VCO supply perturbation, the SSPLL returns to its stable locked frequency in about 5 μsec.frequency-locked loop (FLL) | integer-N PLL | phase noise | Phase-locked loop (PLL) | sub-samplingconference paper10.1109/VLSI-TSA/VLSI-DAT57221.2023.101342002-s2.0-85163003087https://api.elsevier.com/content/abstract/scopus_id/85163003087