Dept. of Electr. Eng., National Taiwan Univ.Hsu, M.-Y.M.-Y.HsuChang, H.-C.H.-C.ChangWang, Y.-C.Y.-C.WangLIANG-GEE CHEN2018-09-102018-09-102001https://www.scopus.com/inward/record.uri?eid=2-s2.0-0035016247&doi=10.1109%2fISCAS.2001.921053&partnerID=40&md5=72d91e7e6228777d31b79ee1040e5228http://scholars.lib.ntu.edu.tw/handle/123456789/292079In this paper, we present a scalable module-based architecture for block matching motion estimation algorithm of MPEG-4. The basic module comprises one set of processing elements based on one-dimensional systolic array architecture. To support various applications, modules of processing elements can be configured to form the processing element array to meet the requirements, such as variable block size, search range and computation power. And this proposed architecture has the advantage of few I/O port counts. Based on eliminating unnecessary signal transitions in the processing element, power dissipation of datapath can be reduced to about half without decreasing the picture quality. © 2001 IEEE.application/pdf373855 bytesapplication/pdfBlock matching motion estimation; Computation power; Picture quality; Processing elements; Proposed architectures; Signal transition; Systolic array architecture; Variable block size; Motion Picture Experts Group standards; Computer architecture; Image quality; Motion estimation; Switching circuits; Systolic arrays; Motion estimation; Image compression; Polygon matching; Power dissipationconference paper10.1109/ISCAS.2001.921053