Su C.-WYu C.-CLiu C.-JWeng C.-Y.VITA PI-HO HU2022-04-252022-04-25202102714310https://www.scopus.com/inward/record.uri?eid=2-s2.0-85108998175&doi=10.1109%2fISCAS51556.2021.9401245&partnerID=40&md5=2c2e6b4da6c7d0400a59c3ee46f57a9fhttps://scholars.lib.ntu.edu.tw/handle/123456789/607351Continued scaling of the interconnect geometry increases the metal resistance which degrades the performance of SRAM in advanced technology nodes. We propose an energy-efficient multi-tiers monolithic 3D (M3D) SRAM cell design with stacked 2D material nanosheet FETs to release the impact of metal line resistance. Considering the 2nm node design rules, the 3-tier M3D SRAM cell with stacked MoS2 FETs shows a 42% reduction in cell area, 49% improvement in read access time, and 68% improvement in energy-delay product. The energy- and area-efficient high-performance 3-tier M3D SRAM cell enables intelligent functionalities for the area and energy-constrained edge computing devices. ? 2021 IEEE2-D materialArea efficiencyEnergy efficiencyMonolithic 3-D (M3D)SRAMCellsCytologyLayered semiconductorsMolybdenum compoundsAdvanced technologyComputing devicesEnergy delay productEnergy efficientEnergy-constrainedInterconnect geometryMetal resistancesTwo-dimensional materialsIntegrated circuit design[SDGs]SDG7conference paper10.1109/ISCAS51556.2021.94012452-s2.0-85108998175