Yu-Yin ChenEn-Jui ChangHsien-Kai HsinKun-Chih ChenAn-Yeu (Andy) WuAN-YEU(ANDY) WU吳安宇2019-10-242019-10-24201710459219https://scholars.lib.ntu.edu.tw/handle/123456789/427728Network-on-Chip (NoC) is the regular and scalable design architecture for chip multiprocessor (CMP) systems. With the increasing number of cores and the scaling of network in deep submicron (DSM) technology, the NoC systems become subject to manufacturing defects and have low production yield. Due to the fault issues, the reduction in the number of available routing paths for packet delivery may cause severe traffic congestion and even to a system crash. Therefore, the fault-tolerant routing algorithm is desired to maintain the correctness of system functionality. To overcome fault problems, conventional fault-tolerant routing algorithms employ fault information and buffer occupancy information of the local regions. However, the information only provides a limited view of traffic in the network, which still results in heavy traffic congestion. To achieve fault-resilient packet delivery and traffic balancing, this work proposes a Path-Diversity-Aware Fault-Tolerant Routing (PDA-FTR) algorithm, which simultaneously considers path diversity information and buffer information. Compared with other fault-tolerant routing algorithms, the proposed work can improve average saturation throughput by 175 percent with only 8.9 percent average area overhead and 7.1 percent average power overhead. © 2016 IEEE.fault-tolerant adaptive routing; Network-on-Chip (NoC); path diversity; selection strategy[SDGs]SDG9Fault tolerance; Network architecture; Network routing; Routing algorithms; Servers; Traffic congestion; Adaptive routing; Deep sub-micron technology; Fault tolerant routing; Fault-tolerant routing algorithm; Network-on-chip systems; Network-on-chip(NoC); Path diversity; selection strategy; Network-on-chipjournal article10.1109/tpds.2016.25884822-s2.0-85013096153