Lin C.-YHung Y.-TWang T.-JTSUNG-HSIEN LIN2021-09-022021-09-02202101936530https://www.scopus.com/inward/record.uri?eid=2-s2.0-85102367059&doi=10.1109%2fISSCC42613.2021.9365821&partnerID=40&md5=5877b00298ab917f0d3e123a2d0945a7https://scholars.lib.ntu.edu.tw/handle/123456789/581175A compact, low-power, low-jitter clock system supporting multiple output frequencies is required in many applications. Using several PLLs to generate multiple frequencies consumes large power and chip area [1]. Alternatively, fractional output dividers (FODs) can be employed (Fig. 29.1.5, top) to generate multiple outputs [2]-[5]. In an FOD, the fractional division is realized by dithering a multi-modulus divider (MMD). The digital-to-time converter (DTC) is used to compensate for the quantization error due to dithering. However, the DTC characteristic is PVT sensitive and requires calibration to mitigate the variation. Prior work adopted additional replica DTCs to realize the DTC gain calibration [2]. Since DTC often dominates power and area in an FOD design, extra DTCs lead to large power and area penalties [2], [3]. Furthermore, mismatch among replica and main DTCs degrades FOD performance. ? 2021 IEEE.Networks (circuits); Solid state devices; Background calibrations; Fractional division; Gain calibration; Low jitter clock; Multi-modulus divider (MMD); Multiple frequency; Multiple outputs; Quantization errors; Calibrationconference paper10.1109/ISSCC42613.2021.93658212-s2.0-85102367059