Chou M.-HSHEN-IUAN LIU2021-09-022021-09-02202115497747https://www.scopus.com/inward/record.uri?eid=2-s2.0-85103459548&doi=10.1109%2fTCSII.2020.3025187&partnerID=40&md5=348eff782a803516d962fb2e5961cdachttps://scholars.lib.ntu.edu.tw/handle/123456789/581132A 2.4 GHz type-I phase-locked loop with foreground loop bandwidth calibration is presented. A successive approximation method is presented to calibrate the loop bandwidth by digitally adjusting the switch size of the master-slave sampling filter. This brief is fabricated in 45 nm CMOS technology. Its active area is 0.013 mm2. The power consumption is 3.6 mW at 2.4 GHz for a supply of 0.9 V. The integrated jitter over 1 kHz to 100 MHz is 3.6 ps. With the supply voltage of 0.88V0.92V, the variation of the loop bandwidth is reduced from 18.7% to 4.6% by using the loop bandwidth calibration. ? 2004-2012 IEEE.Closed-loop bandwidth calibration; Phase-locked loop; Type-IApproximation theory; Binary alloys; Calibration; Vanadium alloys; 45 nm cmos; Active area; I-phase; Loop bandwidth; Master slave; Successive approximation methods; Supply voltages; Switch size; Bandwidthjournal article10.1109/TCSII.2020.30251872-s2.0-85103459548