吳安宇臺灣大學：電子工程學研究所游志強Yeo, Jih-ChiangJih-ChiangYeo2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57603里德所羅門 (Reed Solomon, RS) 碼是一種通道編碼技術，在錯誤更正與維護資料正確性上扮演著重要的角色。RS碼一直被廣泛地使用在各種不同的應用上。對於要求高資料傳輸率的系統，大部分的RS解碼器設計，都採用平行式資料處理架構來實現高速ASIC晶片。而對於某些較低速的應用，例如DVB-T等，則有人使用fine-grained 有限場處理單元 (processing element, PE) 搭配DSP core作為控制核心，可藉由改變處理單元的使用量來變換資料處理速率與動態功率消耗。近來，可動態重規劃 (dynamically reconfigurable) 的VLSI電路架構已漸漸受到重視，它可同時兼顧ASIC的高效能與DSP的高彈性。 在本論文中，我們設計了一個coarse-grained統一式有限場處理單元，並以此建構出一個可動態重規劃之RS解碼器。此解碼器比ASIC式設計擁有更高的應用彈性，以及比DSP式設計具有更高的處理效能。我們提出了Multi-Symbol-Sliced (MSS)資料流處理架構，可在不同的資料傳輸率與動態功率消耗之間做取捨(tradeoff)。對於一個使用m個PE的MSS解碼架構而言，可以被動態重規劃在1-PE、2-PE、…、(m/2)-PE與m-PE的操作模式，提供不同的資料傳輸率與動態功率消耗。 我們提供了一個4-PE的可動態重規劃RS解碼器作為設計原型(prototype design)。在不同操作模式下，可動態改變資料傳輸率與功率消耗，以適用於各種不同系統上。從佈局後NanoSim模擬的結果顯示，這樣一個可動態重規劃的RS解碼器在不同操作模式下，其資料傳輸率與動態功率消耗之間呈現正向線性關係，讓使用者得以在高傳輸率與低功率消耗之間作動態取捨。此解碼器在1-PE、2-PE與4-PE操作模式下，可提供140Mbps/18.91mW、280Mbps/28.77mW 與560Mbps/48.47mW的資料傳輸率/動態功率消耗。除此之外，使用gated clocking設計，我們可更進一步節省28 ~ 56%的功率消耗。Reed-Solomon (RS) codes play an important role in providing the error correction and the data integrity in various communication/storage applications. For high-speed applications, many RS decoders are implemented as dedicated ASICs based on parallel architectures, which can deliver high data throughput rate. For lower-speed applications, some RS decoders are implemented using fine-grained processing elements (PE) controlled by a programmable DSP core, which can provide high flexibility. Recently, the reconfigurable (RC) VLSI architectures become attractive since it can retain both flexibility and speed performance. In this thesis, based on a new coarse-grained PE, we develop the dynamically reconfigurable RS decoding architecture, which provides better flexibility and higher performance than ASIC-type and DSP-type designs, respectively. We propose the Multi-Symbol-Sliced (MSS) data-path structure, which supports the tradeoff between the data throughput rate and the power consumption. We design one m-PE architecture based on a coarse-grained unified finite-field Processing Element (PE). The m-PE architecture can be dynamically reconfigured to operate in 1-PE, 2-PE, …, m/2-PE and m-PE modes, which can support various requirements of the data throughput rate and the energy efficiency. In addition, by using the gated-clocking scheme, we can enhance the power saving greatly. We demonstrate a prototyping design using four processing elements, which can be dynamically reconfigured to operate in 1-PE, 2-PE and 4-PE mode with 140Mbps/18.91mW, 280Mbps/28.77mW and 560Mbps/48.47mW data throughput rate/power consumption, respectively.List of Figures 2 List of Tables 3 Abstract 1 Chapter 1 Introduction 2 1.1 Review of Reed-Solomon Codes 2 1.2 Motivation and Objective 4 1.3 Thesis Organization 6 Chapter 2 Design of Unified Finite-Field Processing Element 7 2.1 Syndrome Calculation 8 2.2 Modified Euclidean Algorithm for Solving Key Equation 10 2.3 Error Correction 13 2.4 Unified Finite-Field Processing Element 16 Chapter 3 Dynamically Reconfigurable Reed-Solomon Decoder 18 3.1 Dynamically Reconfigurable RS Decoder Design Base on Unified PE 18 3.2 Fully Expending (m = 2t) RS Decoder Design Base on Unified PE 20 3.3 Single-PE (m = 1) RS Decoder Design Base on Unified PE 21 3.4 m-PE RS Decoder with Direct-Mapping Data-Path Architecture 22 3.5 Proposed Multi-Symbol-Sliced (MSS) Data-Path Architecture 24 Chapter 4 Operations of Dynamically Reconfigurable Property 27 4.1 Operations of Dynamically Reconfigurable RS Decoder Using Four PEs 27 4.1-1 Full-Run (4-PE) Mode 28 4.1-2 Half-Run (2-PE) Mode 28 4.1-3 Single-PE Mode 29 4.2 Dynamically Reconfigurable Property for d-PE Mode 30 Chapter 5 Performance and Comparison 32 5.1 Decision of m-PE MSS Data-Path Architecture 32 5.1-1 Theoretical Performance Analysis of m-PE design in Different Run-Time Modes 32 5.1-2 Synthesized Data throughput Rate Analysis 33 5.2 Prototyping RS Decoder Implementation with 4-PE MSS Data-Path Architecture 34 5.2-1 Dynamic Power Analysis 35 5.2-2 Applications of the Prototyping Design 37 5.2-3 Performance Comparison with DSP-type Designs 38 Chapter 6 Conclusions 40 References 41697783 bytesapplication/pdfen-US里德所羅門解碼重規劃動態有限場處理單元Reed-Solomondecoderreconfigurabledynamicallyfinite-fieldprocessing element[SDGs]SDG7thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57603/1/ntu-94-R92943008-1.pdf