李泰成臺灣大學：電子工程學研究所曹盛煌Tsao, Sheng-HuangSheng-HuangTsao2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57255這論文包含五個章節。最主要這論文的方向和目的是去分析和設計以及實現一個高速的資料時脈回復電路，且此電路是應用於光纖通訊接收器，且切實的使用了積體化、低成本、低功率的互補金氧半電容電晶體製程去實現它。 這本論文主要環繞在針對兩種不同型態的資料時脈回復電路去做分析其原理並用實際電路去實現它。這兩種電路並都使用0.35-μm互補金氧半電容電晶體製程去實現，在低成本的製程實現其高速應用。這兩種資料時脈回復電路主要的差別在於其相位偵測器型態的差別，例如：線性的相位偵測器、非線性的相位偵測器。並且在電路的設計分析上會去討論這兩者應用於電路上的差別。 第二章的部分，我們會針對資料時脈回復電路去分析其設計原理以及在設計資料時脈回復電路中所必須克服的一些關鍵元件，例如：相位偵測器、頻率偵測器以及壓控震盪器。和傳統鎖相迴路不同的地方在於此資料時脈回復電路操作於不回復至零的隨機序列資料，有別於週期性資料，在電路設計上不同於傳統鎖相迴路。 在第三章中，介紹的是第一個實現的資料時脈回復電路，此電路是設計成能操作於1.25-Gb/s 的隨機資料，在此電路中，使用的架構為雙迴路系統的資料時脈回復電路，其特點在於不需要額外的參考時脈耗損，也就是此電路能夠判別頻率的差距，也就是使用了鎖頻迴路去做資料頻率的偵測。此外，這邊應用的相位偵測器為線性的相位偵測器且使用了兩階層的壓控震盪器。 第四章則是介紹了非線性資料時脈回復電路，也是使用0.35-μm互補金氧半電容電晶體製程去實現。在此電路中使用了另一種型態的壓控震盪器去實現高頻且有良好的相位雜訊表現，能夠達到最高為1.60-Gb/s且最低為1050-Mb/s 的涵蓋範圍。 最後，則是對這兩種型態的資料時脈回復電路做總結和討論。This thesis contains five chapters. The research objective of this thesis is to analyze, design, and implement high-speed CDR circuits for optical fiber receivers that can be readily implemented in an integrated, low-cost, low-power CMOS technology. Our primary contributions to this research include the design methodology and implementation of two CDR circuits fabricated in both CMOS 0.35-μm technologies using linear phase detector (LPD) and binary phase detector (BPD) and we compare and analysis the difference of the two CDR circuits. Chapter 2, we describe the theorem of clock and data recovery (CDR) circuit. Several architectures and some building blocks of CDR are discussed, including phase detector (PD), frequency detector (FD) for random data, and voltage-controlled-oscillator (VCO). . The first CDR circuit in CMOS 0.35-μm technology to support a data rate of 1.25-Gb/s is described in Chapter 3. The frequency lock loop (FLL) without a reference clock is integrated in the CDR. We will discuss the architecture of the CDR based on a phase-locked loop. The building blocks for system are discussed. The building blocks are comprised of a two-stage ring oscillator, a linear phase detector (LPD), and a full-rate frequency detector. Chapter 4 presents the bang-bang CDR fabricated in CMOS 0.35-μm technology to support a data rate from 1050-Mb/s to 1.60-Gb/s with a phase-locked loop (PLL) for frequency acquisition. In this chapter, we also present the analysis of bang-bang loop and some concepts of PLL. Finally, conclusions and discussions are given in Chapter 5.Table of Contents I List of Figures IV List of Tables VIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 2 Chapter 2 Clock and Data Recovery System 4 2.1 General Considerations 5 2.1.1 Open-Loop CDR Architectures 5 2.1.2 Phase-Locking CDR Architectures 7 2.2 CDR Architectures 9 2.2.1 Full-Rate and Half-rate Architectures 9 2.2.2 Referenceless and Referenced CDR Architectures 10 2.3 Clock and Data Recovery Building Block 14 2.3.1 Frequency Acquisition 14 2.3.2 Voltage-Controlled Oscillator 16 2.3.3 Phase Detector 21 Chapter 3 A Linear-Type Clock and Data Recovery Design and Implementation 27 3.1 Motivation 27 3.2 Linear Model Analysis of CDR 27 3.2.1 System Considerations 27 3.2.2 CDR Parameter Design 29 3.3 Architecture 31 3.4 Circuit Design and Simulation Result 32 3.4.1 Preamplifier 33 3.4.2 Phase Detector (PD) 34 3.4.3 Charge Pump (CP) 42 3.4.4 Frequency Detector (FD) 44 3.4.5 Voltage-Controlled Oscillator (VCO) 45 3.4.6 Loop Filter (LPF) 50 3.5 System Simulation Results 53 3.5.1 Behavioral Simulation Results 54 3.5.2 Transistor-Level Simulation Results 56 3.6 Measurement 58 3.6.1 Input/Output Interface 58 3.6.2 Test Setup 60 3.6.3 Experiment Result 62 Chapter 4 A Binary-Type Clock and Data Recovery Design and Implementation 65 4.1 Motivation 65 4.2 Architecture 66 4.3 Circuit Design and Simulation Result 67 4.3.1 Phase Detector (PD) 67 4.3.2 Voltage-Controlled Oscillator (VCO) 69 4.4 Measurement 72 4.4.1 Test Setup 73 4.4.2 Experiment Result 74 Chapter 5 Conclusion 79 Bibliography 80en-US時脈資料回復電路CDRthesis