Self-starting and overclocking a harmonically mode-locking WRC-FPLD with a dual-loop feedback controller for 10 Gb s-1 pulse-data transmission

Lin, C.-J.C.-J.LinChi, Y.-C.Y.-C.ChiGONG-RU LIN2020-06-112020-06-112013https://scholars.lib.ntu.edu.tw/handle/123456789/500283Self-starting and overclocking a harmonically mode-locking WRC-FPLD with a dual-loop feedback controller for 10 Gb s-1 pulse-data transmissionjournal article10.1088/1612-2011/10/6/0650012-s2.0-84879076692https://www.scopus.com/inward/record.uri?eid=2-s2.0-84879076692&doi=10.1088%2f1612-2011%2f10%2f6%2f065001&partnerID=40&md5=b6bd0e3808dddd2078b1ce3181bff344