臺灣大學: 電子工程學研究所黃俊郎楊攸凱Yang, Yu-KaiYu-KaiYang2013-04-102018-07-102013-04-102018-07-102011http://ntur.lib.ntu.edu.tw//handle/246246/256749　　在奈米製程下，晶片內網路(network-on-chip)被發表來解決電晶體數量快速成長與積體電路設計複雜度上升的問題。晶片內網路的效能良好關鍵於有高效率且無鎖死(deadlock-free)的路由。在這篇論文中，我們提出了一個可配合任何自適應性路由演算法(adaptive routing algorithm)的路徑選擇策略並提升效能。 　　聰明容錯路徑(Smart Fault-tolerant Path)的概念是當數據封包經自適應性路由演算法路由回傳多條可以通行的路徑時，盡可能地選擇出一條可容錯的路徑，讓數據封包可以順利往目的地路由，避開錯誤的路由器。除了有容錯能力，實驗結果顯示，無論是在平均延遲和消耗功率，本文提出的如何選擇策略應用到奇偶路由演算法(Odd-Even routing algorithm)優於其他確定性(deterministic)和自適應性路由演算法。Networks-on-Chip (NoC) have been proposed to solve increasing scale and complexity of designs in nano-scale VLSI designs. Efficient and deadlock-free routing is critical to the performance of Networks-on-Chip. In this thesis, we proposed an approach, Smart Fault-tolerant Path, can be coupled to any adaptive routing algorithm to improve the performance. The concept of Smart Fault-tolerant Path is to choose a fault-tolerant channel that will allow the packet to be routed to its destination along a path that is as free as to avoid faulty router when the routing function returns several admissible output channels. In addition to fault-tolerant ability, the proposed selection strategy applied to the Odd-Even routing algorithm outperforms other deterministic and adaptive routing algorithms both in average delay and energy consumption from experimental results.981360 bytesapplication/pdfen-US晶片網路容錯Network on ChipFault-Tolerant[SDGs]SDG7thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256749/1/ntu-100-R98943099-1.pdf