Li, Chi-KangChi-KangLiYeh, Po-ChunPo-ChunYehYu, Jeng-WeiJeng-WeiYuLUNG-HAN PENGYUH-RENN WU2018-09-102018-09-10201300218979http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000326639200046&KeyUID=WOS:000326639200046http://scholars.lib.ntu.edu.tw/handle/123456789/377756https://www.scopus.com/inward/record.uri?eid=2-s2.0-84887270932&doi=10.1063%2f1.4827190&partnerID=40&md5=06b31318c4dcc5168b707906da691ba2A three-dimensional finite element solver is applied to investigate the performance of Ga2O3/GaN nanowire transistors. Experimental nanowire results of 50 nm gate length are provided to compare with the simulation, and they show good agreement. The performance of a shorter gate length (<50 nm) is studied and scaling issues of the short-channel effect are analyzed. With a better surrounding gate design and a recessed gate approach, the optimal conditions for a 20 nm gate length are explored in this paper. © 2013 AIP Publishing LLC.Gate length; Nanowire transistors; Optimal conditions; Recessed gate; Short-channel effect; Surrounding-gate; Three dimensional finite elements; Nanowires; Gallium nitridejournal article10.1063/1.48271902-s2.0-84887270932WOS:000326639200046