An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing

S.-W. ChangJ.-L. HuangJIUN-LANG HUANG2018-09-102018-09-102006-08http://scholars.lib.ntu.edu.tw/handle/123456789/325754An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testingconference paper