Cache design for eliminating the address translation bottleneck and reducing the tag area cost

Dept. of Comput. Sci. & Inf. Eng., National Taiwan Univ.Chang, Yen-JenYen-JenChangLai, FeipeiFeipeiLaiRuan, Shanq-JangShanq-JangRuan2007-04-192018-07-052007-04-192018-07-052002-09http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021064application/pdf1371253 bytesapplication/pdfen-USCache design for eliminating the address translation bottleneck and reducing the tag area costjournal article10.1109/ICCD.2002.1106791http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021064/1/01106791.pdf