指導教授：陳中平臺灣大學：電子工程學研究所張廷愷Chang, Ting-KaiTing-KaiChang2014-11-302018-07-102014-11-302018-07-102014http://ntur.lib.ntu.edu.tw//handle/246246/263902　　本論文中提出了兩種實現高速低功率逐漸趨近式類比數位轉換器的技術，並且透過實際的晶片下線與實際量測驗證，證實所提出的電路設計技術可以有效的提升電路的操作速度以及降低整體電路的功率消耗。所提出的電路設計技術以及晶片實作成果簡述如下： 　　第一個技術為使用電荷分享來實現的管線式架構逐漸趨近式類比至數位轉換器，本架構使用被動元件電容來進行兩級訊號的傳遞，避免了運算放大器的使用，因此整體電路的功率消耗將大幅度的減少。本次設計使用台積電90奈米製程製作，實現一顆9位元，每秒1億次取樣的逐漸趨近式類比至數位轉換器。量測結果在輸入頻率為1M時，當操作頻率分別為10MS/s、20MS/s、50MS/s以及100MS/s時，其ENOB分別為7.33位元、7.27位元、6.92位元以及6.57位元。同時在100MS/s的操作頻率且1伏特的操作電壓時，其功率消耗為2.2毫瓦，FoM為231fJ/conversion-step。 　　第二個技術為多使用一組共模電壓來當作參考電壓以減少電容陣列的整體面積，同時利用電容電流落後於電壓的特性，在切換上作了一些改變，使的在第二位元切換時的電壓值不需要經由重新分布，即可到達目標的電壓值。藉由此方法，除了可以將電容陣列減少50%，同時還可以大幅降低第二位元的穩定時間。本次設計同樣使用台積電90奈米製程製作，實現一顆10位元，每秒1億次取樣的逐漸趨近式類比至數位轉換器。量測結果在輸入頻率為1M時，當操作頻率分別為10MS/s、50MS/s以及100MS/s時，其ENOB分別為7.42位元、7.57位元以及7.32位元。同時在100MS/s的操作頻率且1伏特的操作電壓時，其功率消耗為1.6毫瓦，FoM為100fJ/conversion-step。This dissertation proposes two circuit design techniques for high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-and-concept prototypes, the proposed techniques are able ti improve the operating speed and decrease total circuit power consumption. The proposed techniques and chip measurement results are sketched as follows: The first technique is using charge-sharing method to achieve a Pipelined SAR ADC, this architecture using passive components capacitors for second stage sampling without using OP amplifiers, so the power consumption can be decreased greatly. A 9-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 20MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.33 bits, 7.27 bits, 6.92 bits and 6.57 bits. The ADC consumes 2.2mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 231fJ/conversion-step. The second technique is adding a for reference to decrease the area of capacitor array, also we using the nature of capacitor that current will lagging the voltage, we make some change at switching, so we can achieve the target voltage without charge redistribution, we call this method “voltage-jumping” method. By using this method, we can not only decrease the capacitor array area by 50%, but also reduce the settling time of second bit. A 10-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.42 bits, 7.57 bits and 7.32 bits. The ADC consumes 1.6mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 100fJ/conversion-step.誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS v LIST OF FIGURES ix LIST OF TABLES xv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis organization 1 Chapter 2 Fundamental of Analog-to-Digital Converters 3 2.1 Introduction 3 2.2 ADC Performance metrics 3 2.2.1 Differential Nonlinearity (DNL) 3 2.2.2 Integral Nonlinearity (INL) 4 2.2.3 Signal to Noise Ratio (SNR) 5 2.2.4 Signal-to-(Noise + Distortion) Ratio (SNDR) 7 2.2.5 Resolution and Effective Number of Bits (ENOB) 8 2.2.6 Spurious-Free Dynamic Range (SFDR) 8 2.2.7 Figure of Merit (FoM) 9 2.3 Basic SAR ADC introduction 10 2.3.1 Introduction 10 2.3.2 Basic SAR ADC 11 Chapter 3 The Proposed Charge-Sharing Two-Step High Speed SAR ADC. 13 3.1 Introduction 13 3.2 Proposed SAR ADC 18 3.2.1 Conventional SAR ADC 18 3.2.2 Proposed Charge-Sharing Two-Step SAR ADC 20 3.2.3 Circuit Implement 26 3.3 Layout and Simulation Results 40 3.3.1 Post-simulation Results 40 3.3.2 Power Consumption Analysis 42 3.3.3 Layout Implementation 43 3.3.4 Summary 44 3.4 Experimental Results 45 3.4.1 Introduction 45 3.4.2 Measurement Environment setup 45 3.4.3 PCB Layout 46 3.4.4 Measurement Result 49 3.5 Performance Discussion 55 3.5.1 Delay Problem 55 3.5.2 Sampling Problem 58 3.5.3 Comparator Offset Issue 62 3.5.4 Vref Inductance Problem 64 3.6 Summary 67 Chapter 4 The Proposed Voltage-Jumping Switching Architecture High Speed SAR ADC 68 4.1 Introduction 68 4.2 Proposed SAR ADC 69 4.2.1 Proposed Architecture 69 4.2.2 Circuit Implement 75 4.3 Layout and Simulation Results 87 4.3.1 Post-simulation Results 87 4.3.2 Prior Comparison 89 4.3.3 Power Consumption Analysis 90 4.3.4 Layout Implementation 91 4.3.5 Summary 92 4.4 Experimental Results 93 4.4.1 Introduction 93 4.4.2 Measurement Environment setup 93 4.4.3 PCB Layout 94 4.4.4 Measurement Result 96 4.5 Performance Discussion 99 4.6 Summary 101 Chapter 5 Conclusion and Future Work 103 5.1 Conclusions 103 5.2 Future work 1045329823 bytesapplication/pdf論文公開時間：2017/08/21論文使用權限：同意有償授權(權利金給回饋學校)高速低功率逐漸趨近式類比至數位轉換器thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/263902/1/ntu-103-R00943024-1.pdf