Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology.

Wu, An-YeuAn-YeuWuChan, Tsun-ShanTsun-ShanChanAN-YEU(ANDY) WU2020-06-112020-06-111998https://scholars.lib.ntu.edu.tw/handle/123456789/498006Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology.conference paper10.1109/ICASSP.1998.679626https://doi.org/10.1109/ICASSP.1998.679626