Fang, J.P.J.P.FangTong, Y.-S.Y.-S.TongSAO-JIE CHEN2018-09-102018-09-10200609168508http://www.scopus.com/inward/record.url?eid=2-s2.0-33645749898&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/323973In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated. Copyright © 2006 The Institute of Eletronics, Information and Communication Engineers.Buffer insertion; Dominant wide bus; Floorplanning; RoutingAlgorithms; Congestion control (communication); Floors; Mathematical models; Problem solving; Buffer insertion; Dominant wide bus; Floorplanning; Routing; Integrated circuitsjournal article10.1093/ietfec/e89-a.2.5282-s2.0-33645749898