Yao Y.-SHuang C.-CSHEN-IUAN LIU2022-04-252022-04-25202215497747https://www.scopus.com/inward/record.uri?eid=2-s2.0-85111049256&doi=10.1109%2fTCSII.2021.3087364&partnerID=40&md5=77fd98832518671c442f08b2720ca5achttps://scholars.lib.ntu.edu.tw/handle/123456789/607291A wide-range frequency detector (FD) is presented for baud-rate clock and data recovery (CDR) circuits. It achieves a wide frequency capture range, a short lock time, and a low power. By using this FD, a referenceless quarter-rate CDR circuit with a one-tap decision feedback equalizer is fabricated in 40-nm CMOS technology. The active area of this CDR circuit is 0.0999mm2 and its power is 44mW while the data rate is 16.8Gbps. The calculated energy efficiency of this CDR circuit is 2.62pJ/b. ? 2004-2012 IEEE.Baud rateclock and data recoverydecision feedback equalizerfrequency detectorquarter-rateDecision feedback equalizersEnergy efficiencyFinite difference methodTiming circuitsActive areaClock and data recoveryCMOS technologyData ratesFrequency capturesFrequency detectorsLock timeQuarter-rateClock and data recovery circuits (CDR circuits)[SDGs]SDG7journal article10.1109/TCSII.2021.30873642-s2.0-85111049256