臺灣大學: 電子工程學研究所盧奕璋黃勇叡Huang, Yong-RueiYong-RueiHuang2013-04-102018-07-102013-04-102018-07-102010http://ntur.lib.ntu.edu.tw//handle/246246/256860本篇論文將研究三維晶片網路(3D Network-on-Chip, 3D NoC)的溫度議題，及其對於效能的衝擊。由於製程的進步，通訊的複雜度日益增加，因此晶片網路成為單晶片系統或多核心平台內通訊的常用架構。而結合三維積體電路的技術後，三維晶片網路更具有高整合密度、降低通訊延遲時間與消耗功率、以及提升網路頻寬等優點。但三維積體電路由於在晶片內堆疊了數層的電路層，這使得功率密度變為二維積體電路的數倍，並且離散熱片較遠的電路層散熱也較困難，因此三維積體電路的溫度問題較二維積體電路而言將更為嚴峻。由於三維晶片網路具有許多優勢，相關的研究也相當多，但遺憾的是這些研究卻鮮少著墨在溫度問題上。我們發現傳統的三維晶片網路架構，在晶片的最上層，也就是離散熱片最遠的電路層，由於溫度限制的關係，事實上並無法全速運轉，因此整體晶片網路的效能瓶頸是在於溫度限制而非網路頻寬。因此我們提出了路由器共享架構，將上層的路由器移除，而讓處理元件使用匯流排來共享下層的路由器。因為路由器具有高功率密度，就算處在待機狀態仍會顯著的升高晶片溫度，故我們選擇移除這些路由器以換取較低的晶片溫度。根據我們的實驗結果，在85oC的溫度限制下，路由器共享架構可以比傳統的3D NoC架構多處理大約1.4倍的封包，而在80oC的溫度限制下，路由器共享架構更可以比傳統的3D NoC架構多處理大約2倍的封包量。除此之外，路由器共享架構擁有較低的中繼數(hop)，因此具有較低的零負載延遲，並且傳送封包所需的能量也較低。 另外，我們也對熱雜訊做了分析，隨著製程的進步，邏輯門檻(logic threshold)也越來越小，因此雖然熱雜訊在目前的設計中並不會對電路可靠性造成明顯的影響，但在未來的設計中將可能有明顯的影響。我們算出在8nm製程下，若電路溫度到達85oC，大約四天會有一個錯誤，但若電路溫度到達105oC，一天大約會發生五次錯誤，這在要求高可靠性的系統中是不能接受的錯誤率。In this thesis, we study 3D Network-on-Chip(NoC) and analyze how thermal impacts degrade its performance. NoC is regarded as a novel solution for System-on-Chip communications, and 3D NoC technology has more advantages than 2D NoC in many aspects. The advantages include higher IP mapping density, lower network latency, higher bandwidth and lower power consumption. However, the power density of 3D NoC is times of 2D NoC, but the thermal conductivity is smaller. Therefore, the overheated problem will be more serious in 3D NoCs. To solve the issue, we propose a router-sharing architecture for 3D NoC which outperforms existing 3D NoC designs under thermal impacts. According to thermal simulations, in conventional designs, the routers on the top layers far from the heat sink have to be disabled frequently to avoid thermal emergency. Therefore, the proposed architecture removes all routers on the top layers and uses only buses to connect top-layer PEs to the routers underneath. At 85 oC, our architecture receives 1.4 times as many packets when compared to conventional designs. If the temperature constraint is set at 80oC, our architecture can receive 2 times as many packets. In addition, this new architecture is energy-efficient because the average number of hops is reduced. We also study how thermal noise affects circuit reliability. As technology evolves, logic threshold decreases, which makes circuits more sensitive to thermal noise. At the 8nm technology node, if IC temperature reaches 85oC, about one error will occur within four days. If IC temperature reaches 105oC, about five errors will occur in a day, which is unacceptable in terms of circuit reliability. Therefore, the proposed thermal-aware router-sharing architecture would further improve 3D NoC performance in the future.5306882 bytesapplication/pdfen-US三維積體電路三維晶片網路系統晶片網路系統效能分析晶片熱分析3D Network-on-chipnetwork performance analysisthermal analysis3D ICsthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256860/1/ntu-99-R97943139-1.pdf