Yao-Sheng HuPo-Chao HuangHung-Yen TaiHSIN-SHU CHEN2019-10-312019-10-312016https://www.scopus.com/inward/record.uri?eid=2-s2.0-85027676309&doi=10.1109%2fTCSII.2016.2608908&partnerID=40&md5=d1dca3ef4318f952a3a4a9460123296cThis brief presents a 0.9-V 8-bit 800-MS/s energy-efficient two-step successive-approximation register (SAR) analog-to-digital converter (ADC) without an inter-stage residue amplifier. A charge-sharing technique is used to avoid large static current consumption of the residue amplifier and to eliminate the distortion caused by insufficient amplifier output headroom. Besides, a self-triggered latch technique not only saves the digital power but also accelerates the conversion speed by reducing the SAR loop loading. The prototype ADC consumes 1.59 mW at 800 MS/s and achieves a Nyquist signal-to-noise and distortion ratio of 45.8 dB in 40-nm CMOS technology. It results in an figure of merit of 12.5 fJ/c.-s. © 2004-2012 IEEE.Analog-to-digital converter (ADC); charge sharing; self-triggered; successive approximation; two-step[SDGs]SDG7Approximation theory; Energy efficiency; Frequency converters; Signal to noise ratio; Analog to digital converters; Charge sharing; self-triggered; Successive approximations; two-step; Analog to digital conversionjournal article10.1109/tcsii.2016.26089082-s2.0-85027676309