王暉臺灣大學：電信工程學研究所張家祺Chang, Chia-ChiChia-ChiChang2007-11-272018-07-052007-11-272018-07-052004http://ntur.lib.ntu.edu.tw//handle/246246/58773對現代通訊系統而言，一個穩定的本地振盪源是不可或缺的元件。不論是光通訊或是無線通訊，訊號的調變都需要一個低雜訊的訊號源。鎖相迴路技術已發展多年且是最常應用於實現一個品質的本地振盪源。本論文著重於高頻鎖相迴路中較重要的組成元件，壓控振盪器及除頻器的設計。 壓控振盪器在一鎖相迴路中扮演著產生訊號的角色。在鎖相迴路的迴路頻寬外，壓控振盪器的相位雜訊為鎖相迴路之主要雜訊來源。如同許多已發表的文獻指出，當壓控振盪器的振盪頻率上升，其雜訊表現亦會降級。因此，如何產生高頻振盪且不錯的雜訊表現成為我們關心的重點。在本論文中，我們提出了一個有效的方式把振盪頻率提高且有不錯的雜訊表現。我們所提出的架構結合了傳統的交叉耦合壓控振盪器及雙推式架構。藉由使用互補式場效電晶體0.25微米製程，我們成功地設計完成了40GHz雙推式壓控振盪器。此晶片表現出-15-dBm 輸出功率且約1.3GHz可調頻率。相位雜訊在1MHz位移為-83dBc/Hz。 除壓控振盪器外，除頻器是另一實現高頻鎖相迴路之設計瓶頸。因傳統除頻器是用數位觸發器所實現的，而此架構並不適用於高頻運作。本論文介紹高頻的除頻器架構如注入鎖定式及正反饋式除頻器。在本論文中，一個使用砷化鎵0.15微米製程的60GHz除頻器被設計完成。此電路可運作於兩個運作模式，在注入鎖定模式中，其頻寬為650MHz，在正反饋模式中，其頻寬為750MHz。此架構可在低功率消耗下於高頻運作。另一在本文中介紹的正反饋式除頻器使用互補式場效電晶體0.13微米製程，此電路的特色在於可在高頻操作且寬頻。模擬結果顯示此電路在輸入功率約為-7dBm且輸入正反相位產生器4.5dB的損耗下，在18GHz到46GHz的頻率範圍中皆可除頻。 本論文的最後部分介紹了一個適用於無線本地區域網路之單晶鎖相迴路，其流程討論了設計單晶鎖相迴路之考量。由線性系統模擬結果，在許多表現參數的取捨考量下，我們可得到各組成元件的設計參數。最後在電晶體等級的閉路模擬中可得知所設計的鎖相迴路有著穩定的表現。For modern communication system, a stable local oscillation (LO) is an indispensable component. Either optical communication or wireless communication requires a low-noise signal source for the modulation of the transmitted signal. Phase-locked loop (PLL) technique has been developed for decades and is the most frequently adopted to realize a high-quality LO source. This thesis is dedicated to the design of the essential building blocks for a PLL in high frequency, the voltage-controlled oscillator (VCO) and the frequency divider. A VCO plays the role of signal generation in a PLL system. Its phase noise dominates in the frequency domain outside the loop bandwidth. As many published literatures show, the noise performance degrades as the operation frequency arises. Thus, how to generate high-frequency oscillation with great noise performance becomes an issue of concern. In this thesis, we brought out an effective method capable of raising maximum oscillation frequency with good phase noise. The topology proposed combines the conventional cross-coupled VCO and the push-push architecture and by using standard CMOS 0.25-μm process, a 40-GHz push-push VCO is successfully design and measured. This chip demonstrated -15-dBm output power and about 1.3-GHz tuning range. The phase noise is -83 dBc/Hz at 1-MHz offset. Other than VCO, the frequency divider is the design bottleneck for high-frequency PLL since the conventional flip-flop based structure is not suitable for high-speed operation. In this thesis, high-speed frequency divider topologies, such as injection-locked frequency divider and regenerative frequency divider, are described. In this thesis, a 60 GHz divide-by-two frequency is designed and fabricated using GaAs 0.15-μm pHEMT process. The circuit is capable of operating in two modes. The bandwidth is 650 MHz and 750 MHz in injection-locked mode and regenerative mode respectively. This topology demonstrates high frequency operation with little power consumption. The design of a regenerative frequency divider is also demonstrated in the thesis. The circuit adopted CMOS 0.13-μm process and capable of wideband and high-speed operation. The simulation results show that this circuit can function from 18 GHz to 46 GHz with 7-dBm input power while the input balun demonstrates 4.5-dB insertion loss. To manifest the design concern of a fully-integrated PLL, the design of a monolithic PLL for wireless LAN application is presented in the last part of the thesis. From the linear system simulation, each building block is designed to acquire a compromise between versatile tradeoffs. The transistor-level closed-loop simulation demonstrates the stable operation of the designed PLL.Chapter 1 Introduction: Wireless Communication System and RF Front End 1.1 Background and Motivation……………………………………………………...1 1.2 RF Front End and Phase-Locked Loop…………………………………………..1 1.3 Contributions……………………………………………………………………..2 1.4 Chapter Outlines………………………………………………………………….3 Chapter 2 Phase-Locked Loop Fundamentals 2.1 Introduction………………………………………………………………………5 2.2 Figures of Merit for PLL…………………………………………………………5 2.3 Building Blocks…………………………………………………………………..7 2.4 Linear Model for PLL…………………………………………………………..12 2.5 Noise in PLL ……………………………………………………………………13 Chapter 3 Voltage-Controlled Oscillator: Theory and Design 3.1 Introduction…………………………………………………………………..…17 3.2 Figures of Merit for VCO………………...…………………………………..…17 3.3 VCO Fundamentals…………………………………………………………..…18 3.4 VCO Topologies……………………………………………………….……..…21 3.4.1 Cross-Coupled VCO……………………………………………...……..…21 3.4.2 Push-push VCO………………………………………………………....…26 3.5 Circuit Implementations………………………………………………...…....…26 3.5.1 A 40-GHz push-push VCO using 0.25-2568917 bytesapplication/pdfen-USfrequency dividerPLLVCOfrequency synthesizer鎖相迴路頻率合成器壓控振盪器除頻器thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/58773/1/ntu-93-R91942011-1.pdf