Yen, Chia ChenChia ChenYenYeh, Mi YenMi YenYehMING-SYAN CHEN2024-04-032024-04-032023-01-01979835035911428370430https://scholars.lib.ntu.edu.tw/handle/123456789/641745In recent years, several efforts have explored the construction of multi-ported RAMs using on-chip BRAMs within FPGAs to cater to real-time and data-intensive applications. These designs typically involve a collection of data banks (BRAMs) for data storage and a routing mechanism for accessing the most recent data. Prior research primarily concentrated on optimizing the routing method to reduce routing complexity. In contrast, our work focuses on BRAM consumption reduction by optimizing the distribution of data banks. To achieve this objective, we introduce a novel concept of integrating multiple hard/soft switched ports into a multi-ported RAM design, denoted as IMPC. This integration aims to minimize BRAM usage for temporal-multiplexing workloads on FPGAs. The framework relies on a predefined set of hybrid hard/soft ported memory instances to construct a specific architectural design by addressing a minimum set packing (MSP) problem for implementation optimization. The experimental results and analysis demonstrate that IMPC outperforms other solutions in terms of memory consumption and logic resource utilization for multi-ported memory configurations on FPGAs.embedded memory | embedded systems | FPGAs | multi-ported memoryconference paper10.1109/ICFPT59805.2023.000282-s2.0-85187549775https://api.elsevier.com/content/abstract/scopus_id/85187549775