Ding-Shiuan ShenSHEN-IUAN LIU2018-09-102018-09-102007-1115497747http://scholars.lib.ntu.edu.tw/handle/123456789/333725A 1.5 GHz spread spectrum clock generator (SSCG) is realized by a fractional N frequency synthesizer with a third-order delta-sigma modulator and a fractional dual-modulus prescaler (FDMP). This FDMP utilizes a fractional division ratio to have a small phase step to improve the jitter performance. This SSCG has been fabricated in a 0.18 um CMOS process, and it consumes 34.2 mW from a supply of 1.8 V. The measured rms jitter is 5.55 ps and the measured electromagnetic interference reduction amount is 14.77 dB. The measured phase noise is -97.18 dBc/Hz at 1 MHz offset. © 2007 IEEE.Delta-sigma modulator (DSM); Low jitter; Prescaler; Spread spectrum clock generator (SSCG)Delta sigma modulation; Electric clocks; Electromagnetic pulse; Frequency dividing circuits; Jitter; Phase noise; Spectroscopy; Delta sigma modulator; Dual modulus prescaler; Electromagnetic interference reductions; Fractional-N frequency synthesizers; Low jitters; Prescalers; Spread spectrum clock generator; Spread-spectrum clock generators (SSCG); Modulatorsjournal article10.1109/TCSII.2008.9199932-s2.0-60649086941WOS:000250992300003