臺灣大學: 電信工程學研究所王暉黃柏智Huang, Bo-JrBo-JrHuang2013-03-272018-07-052013-03-272018-07-052010http://ntur.lib.ntu.edu.tw//handle/246246/253324本論文探討射頻端靜電放電保護電路與低雜訊放大器之設計與實現。其一主題在於利用先進的半導體製程，設計出特性良好的射頻靜電放電保護電路，並應用於60 GHz低雜訊放大器。此架構利用阻抗隔離的方式，形成帶通濾波結構，將靜電防護裝置整合形成一寬頻並且可操作在毫米波使用的靜電放電保護電路，實現在台積電點一三微米金氧半場效電晶體製程上。相較於傳統靜電保護電路，此架構具有非常良好的射頻特性以及靜電保護能力，同時並突破目前積體電路技術瓶頸，可操作於V頻帶，為世界第一個完成於毫米波的射頻靜電防護低雜訊放大器。此外，我們亦提出兩種新式射頻靜電防護架構，應用於5.8 GHz砷化鎵兩微米異質接面双極電晶體製程之放大器上；其一結合放電防護元件形成帶通濾波結構並具八向放電路徑，另一使用雜散電容降低技術且擁有四向放電路徑，此二設計較傳統雙向放電路徑電路皆有更佳的射頻特性及更強大的靜電防護能力。 本論文另一主題為多疊接式放大架構之分析。多疊接組態擁有面積小、高增益之特性，因此在低頻曾被採用來設計功率放大器；但由於多疊接組態在高頻會產生額外的雜訊，因此至今在低雜訊放大器上之應用僅廣泛採用雙電晶體疊接架構。在此，本論文提出一雜訊抑制機制，選擇更小尺寸電晶體當放大單元以降低功耗，並於疊接元件之間加上電感來抑制雜訊並提高高頻穩定度，同時結合多疊接架構高增益的優點，應用於毫米波低雜訊放大器設計；此外，並於台積電點一三微米製程設計一Q頻段三疊接及六五奈米製程設計一V頻段疊接低雜訊放大器做為驗證，此二電路相較於傳統低雜訊放大器，具有更低功耗、低雜訊、高增益且小面積之特性。此Q頻段電路同時為首先完成於毫米波頻段之三疊接組態低雜訊放大器。In this dissertation, the designs and analysis of RF electrostatic discharging (ESD) protections in microwave and millimeter-wave (MMW) amplifiers and MMW multi-cascode low noise amplifiers (LNAs) are investigated. One goal of the dissertation is to design and implement the RF ESD protection circuit with impressive performance in modern compound semiconductor process, and apply to a 60-GHz LNA. Based on impedance isolation approach, the protection circuit incorporates with the ESD device to form a broadband band-pass filter structure at MMW frequencies in TSMC complementary metal-oxide-semiconductor (CMOS) 0.13-μm technology. Compared with conventional designs, this work presents better RF performance and higher ESD robustness. At the same time, it overcomes the design bottleneck of integrated circuits to operate at V-band frequency, and is the first RF ESD-protected LNA in MMW regime. Moreover, two novel RF ESD protection circuits applied to 5.8-GHz amplifiers in 2-μm GaAs based heterojunction bipolar transistor (HBT) process are also proposed. One incorporates with the ESD devices to form a band pass filter structure with good impedance matching, which has eight discharging paths. The other is fabricated with parasitic capacitance reduction technique for the ESD protection, and has four discharging paths. The two amplifiers feature much higher ESD robustness and better RF performance than the conventional design with bi-directional discharging paths. The multi-cascode amplified structure is also described and analyzed in the dissertation. The multi-cascode structure has the advantages of miniature size and high gain. However, since the multi-cascode structure will contribute excess noise at high frequency, only the cascode configuration with two transistors is utilized in recently years. Consequently, a low power multi-cascode structure with noise reduction technique, which incorporates with the high gain characteristic is proposed and employed to the design of millimeter-wave LNAs. For demonstration, a Q-band LNA in CMOS 0.13-μm process with triple-cascode structure and a V-band LNA in 65-nm technology with cascode device are fabricated. The two LNAs feature lower power consumption, better noise figure, higher gain, and more compact size than the conventional LNAs. To the best of our knowledge, the Q-band LNA is the first triple-cascode LNA implemented in MMW frequency.3023666 bytesapplication/pdfen-US射頻端靜電放電保護疊接低雜訊放大器毫米波RF ESD protectioncacodeLNAMMWthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/253324/1/ntu-99-F94942078-1.pdf