Loop latency reduction technique for all-digital clock and data recovery circuits

I-Fong ChenRong-Jyi YangSHEN-IUAN LIU2018-09-102018-09-102009-11http://scholars.lib.ntu.edu.tw/handle/123456789/352094[SDGs]SDG7Loop latency reduction technique for all-digital clock and data recovery circuitsconference paper10.1109/ASSCC.2009.53572472-s2.0-76249098318