Tseng Y.-MYen Y.-CSHEN-IUAN LIU2022-04-252022-04-252021https://www.scopus.com/inward/record.uri?eid=2-s2.0-85106605585&doi=10.1109%2fVLSI-DAT52063.2021.9427357&partnerID=40&md5=ba1edb0795634e410ce2656543498ae4https://scholars.lib.ntu.edu.tw/handle/123456789/607293A digital phase-locked loop (DPLL) with background supply noise cancellation is presented. By using a digital low-dropout regulator and a supply noise cancellation controller, this DPLL can tolerate a supply noise of 150mVPP. The DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.0195mm2 and the total power consumption is 7.23mW from a supply of 1.1V. The minimum measured supply voltage sensitivity of the digitally-controlled oscillator is less than 0.0261 [%-fDCO/%-VDD]. With a 100kHz, 150mVPP sinusoidal supply noise, the measured rms jitter of the DPLL at 2.4GHz is reduced from 56.38ps to 15.72 ps. © 2021 IEEE.digital low dropout regulatordigital phase-locked loopdigitally-controlled oscillatorjittersupply noise cancellationElectric current regulatorsSpurious signal noiseVLSI circuitsVoltage regulatorsCMOS technologyDigital phase locked loopsDigitally controlled oscillatorsLow dropout regulatorSinusoidal supplySupply noiseSupply voltagesTotal power consumptionPhase locked loopsconference paper10.1109/VLSI-DAT52063.2021.94273572-s2.0-85106605585