楊佳玲臺灣大學：資訊工程學研究所黃靖傑Huang, Chin-ChiehChin-ChiehHuang2007-11-262018-07-052007-11-262018-07-052005http://ntur.lib.ntu.edu.tw//handle/246246/54093隨著半導體技術的日益進步，我們可以設計整個系統在一顆晶片上。系統單晶片可以減少整個系統的花費、增加效能、減少功率消耗並且減少晶片的面積。但是也增加了設計整個系統晶片的複雜度。為了要在設計晶片前探究系統單晶片平台，我們設計了一套"系統晶片效能與功率評估平台"。一個系統單晶片平台包括一個微處理器、記憶體結構、連結匯流排、週邊和多個矽智財(IP)。對於一個系統單晶片的設計者而言，最大的挑戰就是在設計流程之前量測效能與功率。這篇論文提出一個系統級時脈精確的效能與功率評估經由高效率的軟硬體共同模擬。With the improvement of semiconductor technology, it is now possible that we could construct the whole system on a single chip (SoC). SoC can reduce overall system cost, increase performance, lower power consumption, and reduce chip size. But it also increases the sys-tem design complexity. To facilitate early design space exploration for platform SoC, we are currently developing a system-level performance/power evaluation framework. A platform- based SoC contains a microprocessor, memory hierarchy, interconnected buses, peripherals,and a set of IP cores. For a platform SoC designer, it is challenging to determine platform components in view of performance and power at the early stage of the design °ow. The proposed system-level simulation framework provides cycle-accurate performance and power evaluation at the system-level through e±cient hardware-software co-simulation.Abstract i 1 Introduction 1 2 Background and Previous Work 4 2.1 SystemC Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 System-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1.1 Design Challenge . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.1.2 SoC Design Flow Overveiw . . . . . . . . . . . . . . . . . . 11 2.2 Hardware-Software Co-simulation . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 SystemC Co-simulation Interfaces . . . . . . . . . . . . . . . . . . . . 16 2.2.2.1 Co-simulation Interfaces . . . . . . . . . . . . . . . . . . . . 17 2.2.2.2 Remote ISS Co-simulation . . . . . . . . . . . . . . . . . . . 17 2.2.2.3 Linked ISS Co-simulation . . . . . . . . . . . . . . . . . . . 19 2.2.2.4 Emulation Interfaces . . . . . . . . . . . . . . . . . . . . . . 21 2.3 Transaction Level Modeling(TLM) . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 Architectural Level Power Modeling . . . . . . . . . . . . . . . . . . . . . . . 25 3 Overview of System-Level Performance/Power Evaluation Framework for SoC 28 4 Design of System-Level Performance/Power Evaluation Framework for SoC 30 4.1 Linked-ISS Co-simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1.1 SystemC Wrapper Architecture . . . . . . . . . . . . . . . . . . . . . 32 4.1.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2.1 Co-simulation Flow . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 Timing-Accurate Co-simulation . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.1 Timing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.2 Timing Synchronization Issues . . . . . . . . . . . . . . . . . . . . . . 37 4.2.3 Scheduling Modi‾cations . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 Transaction-Level Modeling with the AMBA . . . . . . . . . . . . . . . . . . 41 4.3.1 AMBA Model and Architecture Overview . . . . . . . . . . . . . . . 43 4.3.1.1 AMBA Architecture . . . . . . . . . . . . . . . . . . . . . . 44 4.4 Performance Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5 Power Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6 IP Plug-In Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5 Case Study 55 5.0.1 Performance and Power Evaluations . . . . . . . . . . . . . . . . . . . 58 6 Conclusion 62 A How to use the proposed framework 69 A.1 Hardware Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 A.2 Software Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70878831 bytesapplication/pdfen-US系統單晶片效能功率複雜度微處理器記憶體結構矽智財系統級軟硬體共同模擬system on a single chip (SoC)performancepowercomplexitymicroprocessormemory hierarchyIP coressystem-levelhardware-software co-simulationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/54093/1/ntu-94-R92922027-1.pdf