Su G.-YKang Z.-HSHEN-IUAN LIU2022-04-252022-04-252021https://www.scopus.com/inward/record.uri?eid=2-s2.0-85106643711&doi=10.1109%2fVLSI-DAT52063.2021.9427319&partnerID=40&md5=45ec9f77e6fcaa4b0be5ca581906fdcdhttps://scholars.lib.ntu.edu.tw/handle/123456789/607292A digital phase-locked loop (DPLL) using the proposed adaptive loop gain controller (ALGC) is presented. The ALGC uses a spectrum-balancing technique to detect the difference of the high-frequency and the low-frequency powers of the bang-bang phase-frequency detector output. Then, the loop gain of the DPLL is adjusted to minimize the output root-mean-square (RMS) jitter. This DPLL is fabricated in 40-nm CMOS process and its active area is 0.016mm2. Operating at a frequency of 3.2 GHz, the power consumption of the DPLL is 1.5mW from a 1V supply voltage. ? 2021 IEEE.adaptive loop gain controllerand phase noisebang-bang phase-frequency detectordigital phase-locked loopjitterspectrum-balancing techniquePhase comparatorsVLSI circuitsAdaptive loopsBalancing techniquesCMOS processsDigital phase locked loopsHigh frequency HFPhase frequency detectorsRoot mean square jitterSupply voltagesPhase locked loopsconference paper10.1109/VLSI-DAT52063.2021.94273192-s2.0-85106643711