Chao-Ching HungSHEN-IUAN LIU2018-09-102018-09-102011-0615497747http://scholars.lib.ntu.edu.tw/handle/123456789/366440https://www.scopus.com/inward/record.uri?eid=2-s2.0-79960030507&doi=10.1109%2fTCSII.2011.2149610&partnerID=40&md5=7ea0da4e154556e5eb782895764f1f25A 40-GHz fast-locked all-digital phase-locked loop (ADPLL) using a modified bang-bang algorithm is presented. An inductor is used to extend the frequency tuning range of a 40-GHz digitally controlled oscillator. This ADPLL is fabricated by a 90-nm complementary metaloxidesemiconductor process. The measured peak-to-peak jitter and the root-mean-square jitter are 2.622 ps and 303.632 fs, respectively, at 40 GHz. The measured locked times are 1.3 ms and 15 μ without and with the modified bang-bang algorithm, respectively. © 2011 IEEE.All digital; digitally controlled oscillator (DCO); fast locked; phase-locked loop (PLL)Jitter; All digital; All digital phase locked loop; Digitally controlled oscillators; fast locked; Frequency tuning range; Peak-to-peak jitter; Phase Locked Loop (PLL); Root mean square jitter; Phase locked loopsjournal article10.1109/tcsii.2011.21496102-s2.0-79960030507