國立臺灣大學電子工程學研究所黃俊郎2006-07-262018-07-102006-07-262018-07-102004-07-31http://ntur.lib.ntu.edu.tw//handle/246246/20020本計劃的目標為發展單晶片無線收發機中 頻率合成器及類比前端電路的自我測試技 術以及相關電路。希望在不增加太多的晶 片面積和影響系統性能的前提下，能有效 地降低單晶片無線收發機的生產測試發展 時間及生產測試費用。研究項目包括發展 數位至類比與類比至數位轉換器與頻率合 成器的自我測試技術、類比前端電路的迴 路測試技術、系統迴路測試技術以及相關 的電路設。The objective of this sub-project is to develop self-testing techniques and supporting circuitry for the analog communication front-end circuits and the frequency synthesizer. Without sacrificing the system performance and inducing too much chip area overhead, this sub-project aims at reducing, for the single-chip wireless transceiver, both the manufacturing test development time and manufacturing test cost. To reach the goal, the research topics include (1) self-testing techniques for AD/DA converters and frequency synthesizers, (2) loop-back testing for baseband analog circuits, and (3) system-level loop-back testing.application/pdf40016 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所可測試性設計內建自我測 試單晶片無線收發機類比前端電路頻率合成器Design-for-TestabilityBuilt-In Self-TestSingle-chip wireless transceiveranalog front-end circuitsfrequency synthesizerreporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/20020/1/922220E002007.pdf