Huai-Yi HsuAn-Yeu WuJih-Chiang YeoAN-YEU(ANDY) WU吳安宇2019-10-242019-10-24200615497747https://scholars.lib.ntu.edu.tw/handle/123456789/427702https://www.scopus.com/inward/record.uri?eid=2-s2.0-37849187467&doi=10.1109%2fTCSII.2006.882360&partnerID=40&md5=aa83180dc07d3d25e27077ed29fa53a7The Reed-Solomon (RS) code is a widely used forward error correction technique to cope with the channel impairments in fiber communication systems. The typical parallel RS architecture requires huge hardware cost to achieve very high speed transmission data rate for optical systems. This brief presents an area-efficient VLSI architecture of the RS decoder by using a novel just-in-time folding modified Euclidean algorithm (JIT-FMEA). The JIT-FMEA VLSI architecture can greatly reduce the hardware complexity by about 50% compared with the fully expanded parallel RS architecture. Meanwhile, it can achieve very high throughput rate for the 10Gbase-LX4 optical communication system. The proposed RS decoder architecture has been designed and implemented by using 0.18- μ m CMOS standard cell technology at a supply voltage of 1.8 V. The post-layout simulation results show that the design requires only about 20 K gates and can achieve the data processing rate of 3.2 Gb/s at a clock frequency of 400 MHz. © 2006, IEEE. All rights reserved.10Gbase-LX4 optical system; Forward error correction (FEC); just-in-time folding modified Euclidean algorithm (JIT-FMEA); key equation solver (KES); Reed–Solomon (RS) codecDecoding; Error correction; Optical data processing; VLSI circuits; Forward error correction; Key equation solver; Reed-Solomon decoder; Optical communicationjournal article10.1109/tcsii.2006.8823602-s2.0-37849187467