Automatic VLSI Circuit Synthesizer System Vol.1:A Programming Logic Array (PLA) Reduction and Generation System

馮武雄Parng, T. P.T. P.Parng于惠中Chen, S. J.S. J.ChenSun, L. F.L. F.SunFeng, Wu-ShiungWu-ShiungFengYu, Hui-JungHui-JungYu2009-01-212018-07-062009-01-212018-07-061985-09http://ntur.lib.ntu.edu.tw//handle/246246/106153en-USAutomatic VLSI Circuit Synthesizer System Vol.1:A Programming Logic Array (PLA) Reduction and Generation Systemreport