First Demonstration of Monolithic 3D Self-aligned GeSi Channel and Common Gate Complementary FETs by CVD Epitaxy Using Multiple P/N Junction Isolation

Tu, Chien TeChien TeTuLiu, Yi ChunYi ChunLiuHuang, Bo WeiBo WeiHuangChen, Yu RuiYu RuiChenHsieh, Wan HsuanWan HsuanHsiehTsai, Chung EnChung EnTsaiChueh, Shee JierShee JierChuehCheng, Chun YiChun YiChengMa, YichenYichenMaCHEE-WEE LIU2023-08-012023-08-012022-01-01978166548959101631918https://scholars.lib.ntu.edu.tw/handle/123456789/634350Monolithic 3D self-aligned vertically stacked Ge0.75 Si0.25 nanosheet complementary FETs with multiple P/N junction isolation by in-situ doped CVD epitaxy are experimentally demonstrated. The triple P/N junctions using Ge:B/Ge:P multilayers suppress the leakage current without extra dielectric layers. Both the top pFETs and bottom nFETs have the same uniform GeSi nanosheets thanks to the co-optimization of CVD epitaxy and highly selective HNO3 wet etching (selectivity140). Self-aligned GeSi channels and common gate architecture are fabricated as a CMOS inverter with good voltage transfer characteristics. The post-metallization annealing with the low thermal budget of 400°C improves the inverter characteristics such as switching threshold voltage and voltage gain. The self-aligned 3D stacked GeSi nanosheet pFETs on GeSi nanosheet nFETs without wafer bonding, dielectric isolation, and selective epi regrowth can simplify the process for 3D transistor stacking.First Demonstration of Monolithic 3D Self-aligned GeSi Channel and Common Gate Complementary FETs by CVD Epitaxy Using Multiple P/N Junction Isolationconference paper10.1109/IEDM45625.2022.100195322-s2.0-85147513587https://api.elsevier.com/content/abstract/scopus_id/85147513587