李建模臺灣大學：電子工程學研究所白炳川Bai, Bing-ChuanBing-ChuanBai2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57308本論文提出一套可同步壓縮系統晶片的測試資料量與測試時間的技術，此技術包括兩階層的硬體解壓縮架構，以及針對此硬體架構而建立的資料壓縮演算法。在系統晶片內此硬體解壓縮架構，不需改變系統晶片內嵌核心的設計。第一層架構使用可重載狀態之線性回授位移暫存器對於從測試機台輸入的測試資料進行解壓縮，由第一層架構解壓縮的測試資料經過系統晶片內部的測試存取機制到達第二層架構。第二層架構使用測試資料廣播的方式達到資料壓縮的目的，測試資料被廣播到每個內嵌核心，然後執行每個內嵌核心的測試。測試結果經過多輸入埠位移暫存器壓縮之後，壓縮後的測試結果送回測試機台進行分析以了解此系統晶片是否通過測試。針對d695系統晶片基準電路所做的實驗結果顯示，測試資料可減少百分之七十八，測試時間可減少百分之三十八。當測試資料量減少以及測試時間縮短的情況下，對於測試過程所需要的花費將會大大的降低。This thesis presents a novel technique to simultaneously reduce the test data volume and test application time for System-on-Chip. The technique includes two-level hardware architecture and the compression algorithm for deterministic test data. The two-level hardware is inserted into the SOC without modifying the embedded cores. The first level, also called L1, is for the entire SOC. The second level, also called L2, is for every individual IP or core in the SOC. L1 compression is achieved by linear-feedback shift register (LFSR) reseeding. L2 compression is achieved by broadcasting test data to multiple cores. L1 compression reduces test data volume only, and L2 compression reduces test data volume as well as test application time. The experimental results on the d695 SOC shows that 79% of original test data volume is reduced, and 39% of original test application time is reduced.摘要 i Abstract ii Table of Contents iii List of Figures v List of Tables vii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Technique and Contributions 3 1.3 Organization 4 Chapter 2 Background 5 2.1 Built-in Self Test (BIST) 5 2.1.1 BIST Architecture 5 2.1.2 Seed Calculation 7 2.2 Code-Based Techniques 8 2.2.1 Fixed-to-Fixed Code 9 2.2.2 Fixed-to-Variable Code 10 2.2.3 Variable-to-Fixed Code 11 2.2.4 Variable-to-Variable Code 13 2.3 Linear-decompression-based Techniques 14 2.3.1 Combinational Linear Decompression 14 2.3.2 Sequential Linear Decompression 17 2.4 Hybrid Methods 22 Chapter 3 Our Proposed Technique 24 3.1 Hardware Architecture for SOC 24 3.2 L1 Decompressor Architecture 26 3.3 L1 Compression Algorithm 32 3.3.1 LFSR reseeding 33 3.3.2 Solve Seeds with Bypass Strategy 35 3.4 L2 Broadcaster Architecture 37 3.5 L2 Compression Algorithm 41 3.5.1 Find Best Compatible Data 45 3.5.2 Generate Header in TAM data 46 3.6 Conclusion 47 Chapter 4 Experimental Result 48 4.1 Core Statistics and Test Data of d695 48 4.2 L2 Test Data Compression 52 4.3 L1 Test Data Compression 58 4.4 Conclusion 60 Chapter 5 Discussion & Future Work 61 5.1 Comparison with Other Techniques 61 5.2 Alternate ATPG test set 62 5.3 Commercial Tools 63 5.4 One-Level vs. Two-Level Compressions 64 5.5 Area Overhead 65 5.6 Relation to [Liao 07] 66 5.7 Future Work 67 Chapter 6 Summary 69 References 701002215 bytesapplication/pdfen-US電腦輔助設計積體電路測試可測試性設計系統晶片測試測試資料壓縮測試時間縮減Computer-aided DesignVLSI TestingTest CompressionSOC TestingTest data compressiontest time reductionDesign for testabilitythesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57308/1/ntu-96-R93943086-1.pdf